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作者： Huang, Hai University of Waterloo

学位级别：博士

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not

关键词： analog predistortion digital predistortion linearization power amplifier under-sampling field programmable gate array

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The Ccap: A New Physical Unclonable Function (Puf) For Protecting Internet Of Things (Iot) And Other Fpga-Based Embedded Systems

The Ccap: A New Physical Unclonable Function (Puf) For Prote...

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作者： Jeff G. Josiah University of Arizona

学位级别：博士

The importance of cybersecurity has grown exponentially over the years due to our highly interconnected world and the evolution of computer threats. These threats – once as simple as annoying computer viruses – are now destructive malware, ransomware, and advanced persistent threats (APT) sponsored by nation states used to steal military secrets, wage industrial espionage, and weaponize the Cyberspace into the 5th domain of future military conflict right behind Land, Sea, Air, and Space. Every device that interfaces with the Internet is a potential target. For instance, the attack surface for Internet of Things (IoT) is expected to expand with an estimated 14.2 billion connected “things” projected to be in use this year alone. These “things” are diverse and include rugged-industrial sensors, personal wearables, in-home appliances, and even some of the vehicles on the road today. Many IoT devices are beginning to utilize field programmable gate arrays (FPGAs) for their processing subsystem due to design flexibility and because FPGAs, as a design element, enable product lifecycle support through aftermarket upgradability of both the computer software (CSCI) and firmware/hardware (FWCI) configuration items. This allows manufacturers to enhance product functionality through over-the-Internet (OTI) or over-the-air (OTA) upgrades. Unfortunately, the increasing use of FPGAs has also brought a major concern of intellectual property (IP) theft and product counterfeiting. To help thwart IP theft, FPGA vendors such as Xilinx and Intel PSG (formerly Altera) provide end-users with the ability to encrypt design bitstreams at rest with a cryptographic key. This encryption key is typically stored in EEPROM, Battery-Backed RAM, or within dedicated Anti-Fuses within the device; however, numerous non-invasive, semi-invasive, and invasive attacks exist that can retrieve the encryption key and compromise the design bitstream. Physical (sometimes referred to as physically) unclonable fun

关键词： Embedded Systems field programmable gate array FPGA Security IoT Physical Unclonable Functions PUFs

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Design and Implementation of Hardware Search Algorithm Based on FPGA

Frontiers in Economics and Management

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Frontiers in Economics and Management 2021年第5期2卷 317-320页

作者： Xi Gao Liyan Zhang

In the design of the switch, the search algorithm is one of the most critical core modules. There are many traditional table entry search methods, mainly: linear search method, binary tree search method, hash table search, etc. These search methods are software search methods based on SRAM, and the common feature is slow search speed. The linear lookup table method needs to traverse all entries in the table; the binary tree search method needs to traverse most nodes in the tree, and the search speed is greatly affected by the depth of the tree; the hash table search method is relatively fast, but with the network speed requirement As it gets higher and higher, hash search still cannot meet the demand for extremely fast search. This text designs and realizes a kind of hardware search algorithm, utilizes the characteristic of FPGA to process the data in parallel, speed up the data search ability greatly, further shorten the switch forwarding delay.

关键词： field programmable gate array Media Access Control Address TCAM

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To retrieve biomedical signals in single channel by FPGA-WeICA platform

影像处理暨通讯期刊

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影像处理暨通讯期刊 2021年第1期13卷 1-5页

作者： Ming-Yen Chen Chung-Young Chen Wei-Lung Geng

Wearable devices were becoming more popular nowadays. Thus, multi-channel measurement of physiological signals had become an inevitable trend. As for traditional technology, time division multiplexing (TDM) cannot achieve real-time measurement using time slots, while frequency division multiplexing (FDM) required additional high-cost hardware and software to in cooperate, since utilized the fundamental frequency signal and the carrier to modulate onto different central frequencies. This research will develop an identification platform to transmit multiple physiological signals on a single channel. A low cost and high retrieval in biomedical signals platform consisted of two parts, one was field programmable gate array (FPGA) as the core processor, and another was wavelet enhanced independent component analysis (WeICA) as a post-signal processing unit. Its advantages can not only remove noise and improve the signal-to-noise ratio (SNR), but also improve noise immunity and reduce costs. For the purpose to evaluate platform in flexibility, reproducibility, and stability, we adopted MIT/BIH ECG normal database as source signals. The absolute correlation coefficient between original and estimated groups, which separated by WeICA results, were 98.3%, 97.8%, 99.5% and 96.8% respectively. Again, we real-time recorded 10 healthy volunteers by 4 physiological measurements experiments, i.e., EMG, ECG, blood pressure and EEG. According to the cost function and correlation coefficient estimation, FPGA and WeICA physiological measurement platform had a high decimation in separating signals blindly and achieved similar ＂multiplexing＂ through single USB 3.0 connection.

关键词： field programmable gate array retrieve biomedical signals independent component analysis

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Beam Steering and Control Algorithm for 5-18GHz Transmit/Receive Module Based Active Planar array

Beam Steering and Control Algorithm for 5-18GHz Transmit/Rec...

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2020 International Conference on System, Computation, Automation and Networking, ICSCAN 2020

作者： Maddegalla, Maheeja Bazil Raj, A Arockia Rao, Gurugubelli Syamala Electronics Engineering Defence Institute of Advanced Technology Pune India Defence Electronics Research Laboratory Hyderabad India

ISBN: (纸本)9781728162027

With the advent of Active Electronically Scanned array (AESA) technology in the design and development of advanced multi-Target handling Radar and Electronic Warfare (EW) systems, a new EW system with a Phased array of a uniform spacing was developed, whose beam can be controlled using adaptive software programs. The critical EW system is recognized with miniaturized Planar arrays using Transmit/Receive modules or T-R modules. The T-R modules use a novel core technology for the development of AESA technology. The planar arrays are miniaturized using multifunctional Monolithic Microwave Integrated Circuits (MMIC) with an inbuilt digital circuitry for beam steering, which requires high quality and different levels of programming using field programmable gate arrays (FPGA's). The AESA generally consists of thousands of T-R modules which can individually spread their signal emissions out across a band of the frequencies and sensitively receive the echoes from target objects, allowing it to broadcast transmitting signals while remaining stealthy and greatly increasing the detection and tracking abilities. Implementation of beam steering and control algorithms has to be designed in the frequency of 5-18 GHz for T-R module based planar arrays. © 2020 IEEE.

关键词： AESA Technology Beam steering field programmable gate array Planar array T-R Module

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Terrain Relative Navigation Enhanced with SAR for Moon's Shadowed Regions

Terrain Relative Navigation Enhanced with SAR for Moon's Sha...

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AIAA Science and Technology Forum and Exposition (AIAA SciTech)

作者： Hidaka, Moeko Takahashi, Masaki Ishida, Takayuki Fukuda, Seisuke Keio Univ Sch Sci Open & Environm Syst 3-14-1 HiyoshiKohoku Ku Yokohama Kanagawa 2238522 Japan Keio Univ Dept Syst Design Engn 3-14-1 HiyoshiKohoku Ku Yokohama Kanagawa 2238522 Japan Japan Aerosp Explorat Agcy Inst Space & Astronaut Sci 3-1-1 YoshinodaiChuo Ku Sagamihara Kanagawa 2525210 Japan

ISBN: (数字)9781624105951

ISBN: (纸本)9781624105951

This study proposes a terrain relative navigation (TRN) method to estimate spacecraft positions in the shadowed regions of the moon with high precision by combining the camera image and the synthetic aperture radar (SAR) data. TRN, which estimates the position of a spacecraft by comparing the preliminary terrain information stored in a database with the observed terrain, is an effective method of correcting the drift errors of inertial measurement units (IMUs). Optical cameras are primarily used for TRN sensors to observe the terrain;however, shadow images do not have enough characteristic points to match with the database. SAR is a form of radar that can generate high-resolution photo-like images, regardless of light conditions. In this study, we propose the use of SAR as navigation sensors and demonstrate effectiveness of SAR.

关键词： Terrain Relative Navigation Synthetic Aperture Radar Remote Sensors Moon Inertial Measurement Unit Extended Kalman Filter Lunar Reconnaissance Orbiter field programmable gate array Planets Autonomous Precision Landing

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ALU and Dependency Manager Using FPGA

ALU and Dependency Manager Using FPGA

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作者： Hashem, Amjad Qusay University of Michigan

学位级别：硕士

In this project, we have researched the design of high-speed processing units through parallel processing scheme. Our design will be used for Real – Time applications such as Data Acquisition, DSP, Real – Time Controllers, etc. This project is introducing a new method to handle the parallel processing, this method will process instructions with respect to the dependencies among all instructions. Having a parallel processing capability allows this design to have extremely fast processing speed. In this project we will review every part of the system, and how it contributes to the performance of the system. Currently FPGAs are used as specialty processing units of systems to boost up the throughput of those systems. Using FPGA to speed up special operations, such as database sorting [1, p. 53], data buffering, and many other function that require either high throughput processing, or low latency processing [2, p. 213], can increase the performance of the system. In addition, the normal design for a processing unit that can be part of a system is pipelining processing scheme. In this project, we present a new processing scheme capable of parallel processing, as well as dependency management, both built in the internal design of the unit. This design will eliminate the need for a dependency management software, which can take extra processing time or force the processor to have to process instruction sequentially. Instead, this design will allow parallel processing and dependency management built in a single integrated processing unit.

关键词： ALU Arithmetic logic unit Dependency manager FPGA field programmable gate array Parallel processing

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Using a model-based systems engineering (Mbse) variant approach for architecting signal processing in a space-based sensor

Using a model-based systems engineering (Mbse) variant appro...

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Accelerating Space Commerce, Exploration, and New Discovery Conference, ASCEND 2020

作者： Gans, Howard D. Cuellar, Robert L3Harris Technologies MelbourneFL32902 United States

ISBN: (数字)9781624106088

ISBN: (纸本)9781624106088

Model-Based Systems Engineering (MBSE) can be used to develop the architecture of a space-based sensor. The process begins with the development of use cases (UCs) of a general system model for a sensor processor which is composed of both hardware and software-based elements. Domain-specific UC’s can then be created and linked to the general level. This process continues through the modeling of variances in system behavior, including activity, sequence and state diagrams. This is done in parallel with the development of structural model instances that represent the configuration of the system for the specific domain being considered. The result is an end-to-end extensible sensor model that can then be applied to analyze the end-to-end signal processing chain. © 2020 The MITRE Corporation. All Rights Reserved.

关键词： Signal Processing Sensor Systems Model Based System Engineering Structural Modeling Structural Analysis field programmable gate array Graphics Processing Unit Small Satellites Data Products

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GF-3 data real-time processing method based on multi-satellite distributed data processing system

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Journal of Central South University 2020年第3期27卷 842-852页

作者： YANG Jun CAO Yan-dong SUN Guang-cai XING Meng-dao GUO Liang College of Geomatics Xi’an University of Science and TechnologyXi’an 710000China National Laboratory of Radar Signal Processing Xidian UniversityXi’an 710071China School of Physics and Optoelectronic Engineering Xidian UniversityXi’an 710071China

Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not *** of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture *** is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the *** from the traditional CS algorithm processing,the system divides data processing into three *** computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each *** method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing ***-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified.

关键词： synthetic aperture radar full-track utilization rate distributed data processing CS imaging algorithm field programmable gate array Gaofen-3

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Design of Narrow Transition Band Digital Filter: An Analytical Approach

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INTEGRATION-THE VLSI JOURNAL 2019年第Sep.期68卷 38-49页

作者： Roy, Subhabrata Chandra, Abhijit Jadavpur Univ Dept Instrumentat & Elect Engn Sect 3Block LBPlot 8 Kolkata 700106 India

Frequency response masking (FRM) approach, is widely used to reduce the transition width of FIR filter which includes several advantages like lower coefficient sensitivity, higher computation speed and low power consumption. This paper proposes a novel interpolated bandpass method (IBM) for the synthesis of linear phase, narrow transition band FIR filter with less complexity. Simulation results have shown the magnitude response of several lowpass FIR filters with narrow transition bandwidth, as designed with the aid of proposed approach. Supremacy of the proposed algorithm has also been established in terms of frequency response characteristics and hardware complexity over a number of state-of-the-art techniques of recent interest. Simulation results have identified an improvement of similar to 18.89%, 44.62%, 38.75%, 41.2% and 29.5% in terms of transition bandwidth when compared with several example filters under consideration. In addition to this, hardware cost resulting from the proposed narrow-band FIR filter is analyzed by implementing it on Artix field programmable gate array (FPGA) chip and consequently power consumption of the resulting filter has been estimated using Xilinx Power Estimator (XPE)-2018.1. Finally, the designed narrow transition band FIR filter is used in filtered-orthogonal frequency division multiplexing (F-OFDM) based quadrature amplitude modulated (QAM) system and the resultant bit error rate (BER) performance has been studied.

关键词： Bandpass filter Bit error rate Finite impulse response filter field programmable gate array Filtered OFDM Low complexity Narrow-band filter Orthogonal frequency division multiplexing Xilinx

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