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Hardware/Software Co-design for a Neural Network Trained by Particle Swarm Optimization Algorithm

NEURAL PROCESSING LETTERS 2019年第2期49卷 481-505页

作者： Tuan Linh Dang Hoshino, Yukinobu Kochi Univ Technol Sch Syst Engn Kochi 7828502 Japan

A co-design architecture for the field programmable gate array (FPGA)-based classification system is proposed. In this architecture, a neural network (NN) is trained by the particle swarm optimization algorithm (PSO). The NN is implemented in hardware, and the PSO training is executed by a processor. The ARM processor and the NIOS II processor are used. This architecture maintains the operating speed of the NN. This approach also has the flexibility to change the parameters or even the PSO algorithm without affecting the FPGA part. Three publicly recognized databases (Iris, Balance-scale, Credit approval) are used to evaluate the system. Experimental results showed that the co-design was successfully implemented. In addition, compared to the NIOS II approach, the ARM approach had the advantages regarding the operating speed and the logic utilization.

关键词： Neural network Particle swarm optimization field programmable gate array ARM processor

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Efficient FPGA Implementation of Multilayer Perceptron for Real-Time Human Activity Classification

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IEEE ACCESS 2019年 7卷 26696-26706页

作者： Gaikwad, Nikhil B. Tiwari, Varun Keskar, Avinash Shivaprakash, N. C. Visvesvaraya Natl Inst Technol Nagpur 440010 Maharashtra India Indian Inst Sci Bengaluru 560012 India

The smartphone-based human activity recognition (HAR) systems are not capable to deliver high-end performance for challenging applications. We propose a dedicated hardware-based HAR system for smart military wearables, which uses a multilayer perceptron (MLP) algorithm to perform activity classification. To achieve the flexible and efficient hardware design, the inherent MLP architecture with parallel computation is implemented on FPGA. The system performance has been evaluated using the UCI human activity dataset with 7767 feature samples of 20 subjects. The three combinations of a dataset are trained, validated, and tested on ten different MLP models with distinct topologies. The MLP design with the 7-6-5 topology is finalized from the classification accuracy and cross entropy performance. The five versions of the final MLP design (7-6-5) with different data precision are implemented on FPGA. The analysis shows that the MLP designed with 16-bit fixed-point data precision is the most efficient MLP implementation in the context of classification accuracy, resource utilization, and power consumption. The proposed MLP design requires only 270 ns for classification and consumes 120 mW of power. The recognition accuracy and hardware results performance achieved are better than many of the recently reported works.

关键词： Human activity recognition multilayer perceptron smart military wearables classifier hardware implementation field programmable gate array

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A novel parallel duty cycle control algorithm for photovoltaic voltage regulator system using FPGA

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MICROPROCESSORS AND MICROSYSTEMS 2019年 65卷 107-120页

作者： Prathap, Joseph Anthony Anandhi, T. S. Vardhaman Coll Engn Dept Elect & Commun Engn Hyderabad India Annamalai Univ Dept Elect & Instrumentat Chidambaram India

In this paper, a novel parallel duty cycle control method is proposed to regulate the load voltage of the photo voltaic (PV) fed DC-DC buck converter. The proposed method concentrates on the control of PV fed DC-DC buck converter by fusing the two duty cycles from maximum power point tracking (MPPT) and digital proportional integral-digital pulse width modulation (DPI-DPWM) through the HDPWM algorithm. The fusion of the MPPT algorithms and DPI-DPWM algorithms achieve high precision in the voltage regulation of the PV fed DC-DC buck converter. The proposed parallel duty cycle control is passed through the HDPWM algorithm to compensate the high clocking frequency demand with the design resolution of 2(10) bits. Further, the design complexity of the HDPWM algorithm is reduced as the resolution of 2(10) bits is split as 2(5) and 2(5) bits for CDPWM and DDPWM respectively. The FPGA based implementation of the proposed parallel duty cycle method includes the synthesizable VHDL code for i) MPPT algorithms, ii) DPI-based DPWM algorithms, iii) Fusing of the MPPT-DPI-DPWM and iv) Passing the fused MPPT-DPIDPWM through the HDPWM algorithm. The Xilinx Spartan 3A DSP, FPGA implementation is suitable for the proposed parallel duty cycle control method. The hardware results validate the satisfactory PV voltage regulation under continuous changing weather conditions. The transient response of INC-DPI-HDPWM seems to have a faster settling time compared to other MPPT-DPI-DPWM methods. Also, its FPGA implementation proves less area in design and low power consumption compared to the existing methods. (C) 2019 Elsevier B.V. All rights reserved.

关键词： field programmable gate array Maximum power point tracking algorithm Digital PI control Digital pulse width modulation techniques DC-DC buck converter

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A framework for high-level simulation and optimization of fine-grained reconfigurable architectures

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SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL 2019年第8期95卷 737-751页

作者： Pasha, Muhammad Adeel Farooq, Umer Siddiqui, Bilal LUMS Dept Elect Engn SBASSE Lahore Pakistan Dhofar Univ Elect & Comp Engn Dept Salalah Oman Purdue Univ Dept Elect & Comp Engn W Lafayette IN 47907 USA

field programmable gate arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.

关键词： High-level simulation embedded systems reconfigurable architectures field programmable gate array

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Cellular Automata with Synthetic Image - A Secure Image Communication with Transform Domain

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DEFENCE SCIENCE JOURNAL 2019年第3期69卷 259-265页

作者： Sundararaman, R. Upadhyay, H. N. Sridevi, A. Sivaraman, R. Anand, V Srinivasan, T. Savithri, S. SASTRA Deemed Univ Thanjavur 613401 India DRDO Combat Vehicles Res & Dev Estab Chennai 600054 Tamil Nadu India

Image encryption has attained a great attention due to the necessity to safeguard confidential images. Digital documents, site images, battlefield photographs, etc. need a secure approach for sharing in an open channel. Hardware - software co-design is a better option for exploiting unique features to cipher the confidential images. Cellular automata (CA) and synthetic image influenced transform domain approach for image encryption is proposed in this paper. The digital image is initially divided into four subsections by applying integer wavelet transform. Confusion is accomplished on low - low section of the transformed image using CA rules 90 and 150. The first level of diffusion with consecutive XORing operation of image pixels is initiated by CA rule 42. A synthetic random key image is developed by extracting true random bits generated by Cyclone V field programmable gate array 5CSEMA5F31C6. This random image plays an important role in second level of diffusion. The proposed confusion and two level diffusion assisted image encryption approach has been validated through the entropy, correlation, histogram, number of pixels change rate, unified average change intensity, contrast and encryption quality analyses.

关键词： Image encryption Confusion Diffusion Cellular automata IWT Synthetic image field programmable gate array

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Real-Time HIL Emulation of Faulted Electric Machines Based on Nonlinear MEC Model

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IEEE TRANSACTIONS ON ENERGY CONVERSION 2019年第3期34卷 1190-1199页

作者： Jandaghi, Behzad Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

In electric machine drive systems, hardware-in-the-loop (HIL) emulation provides accurate testing of actual control system prototypes and protection devices interfaced with the electric machine model on a real-time simulator in a non-destructive environment particularly when faults are studied. A compromise between the model accuracy and computational burden makes the magnetic equivalent circuit (MEC) model ideal for real-time simulation of electric machines. However, satisfying the timing constraints of real-time simulation to accommodate internal machine faults is still challenging due to the nonlinearity and rotation of electric machines. In this paper, the transmission line modeling (TLM) method is utilized to keep the MEC coefficient matrix unchanged during nonlinear iterations. Afterward, for the first time, the entire potential of the TLM method for pre-calculation is exploited by proposing an efficient matrix re-ordering combined with the left-looking Gilbert-Peierls algorithm to minimize the computational burden of the sparse MEC matrix LU decomposition required in each time-step due to rotation. Furthermore, the massive hardware architecture of the field programmable gate array is used as the platform for implementation to fully exploit parallelism. With the proposed MEC-based real-time TLM method, the minimum time-step as low as 500 mu s can be achieved and the results validation with two-dimensional finite element model (FEM) of the commercial Jmag-Designer software shows the accuracy and efficiency of the proposed methodology.

关键词： Fault analysis field programmable gate array hardware-in-the-loop emulation induction motor magnetic equivalent circuit nonlinearity parallel processing real-time systems transmission line modeling

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Adaptive absolute SCORE algorithm for spectrum sensing in cognitive radio

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MICROPROCESSORS AND MICROSYSTEMS 2019年 69卷 43-53页

作者： Nareshkumar, Shanigarapu Bikshalu, Kalagadda Vidya Bharathi Inst Technol Elect & Commun Engn Warangal 506201 Telangana India Kakathiya Univ Elect & Commun Engn Warangal Telangana India

The Cognitive Radio (CR) is one of the significant technology to enhance the spectrum utilization efficiency. The Radio Frequency (RF) spectrum is the most valuable natural resource. Due to an increased usage of the cognitive radio, the sensing issues in spectrum are increasing day by day. The CR is emerging technologies that increase the effectiveness and efficiency of the spread spectrum communication. Generally, the spectrum sensing is based on the energy detection and cyclostationary feature detection. The energy detection is a fundamental basic spectrum sensing technique. However, it performs poorly under a low Signal-to-Noise Ratio (SNR) environment. The cyclostationary based sensing technique improves Primary Users (PUs) detection performance with the high complexity of implementation and hardware utilization. Traditional median and Finite Impulse Response (FIR) filters are utilized complex adder and multiplier, which requires large memory space to store the filter coefficients and more hardware utilization. Hence, these filters have computational complexity and more hardware utilization. To overcome above-mentioned problems, Adaptive Absolute SCORE (AA-SCORE) architecture is designed based on optimal FIR filter for further reducing the system complexity to enhance the spectrum utilization efficiency in CR. In this research, the FIR filter is designed by using Radix-8 and Carry Select Adder (CSLA) for reducing the filter complexity. The proposed method is named as AAS-R8-CSLA architecture. The AAS-R8-CSLA architecture was implemented in the field programmable gate array (FPGA) platform through Verilog code. In order to improve the spectrum utilization efficiency of CR by using AAS-R8-CSLA. The experimental outcome showed that the proposed AAS-R8-CSLA architecture has improved FPGA performance up to 2-3% compared to existing methods like MS and ACS architecture. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Adaptive absolute SCORE Cognitive radio Carry select adder Finite impulse response field programmable gate array

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Joint Polarization Tracking and Equalization in Real-Time Coherent Optical Receiver

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IEEE PHOTONICS TECHNOLOGY LETTERS 2019年第17期31卷 1421-1424页

作者： Zhang, Xu Zeng, Tao Li, Xiang Li, Jie Meng, Lingheng Jiang, Feng Liu, Ziqing Yu, Shaohua Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Hubei Peoples R China Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan 430074 Hubei Peoples R China China Informat Commun Technol Grp Corp State Key Lab Opt Commun Technol & Networks Wuhan 430074 Hubei Peoples R China

We experimentally demonstrate a real-time polarization tracking and equalization method based on the state of polarization detection from the adaptive finite impulse response (FIR) filter coefficients in a polarization division multiplexed (PDM) coherent optical communication system. By calculating the variation of the polarization within a time interval, the polarization rotation speed can be evaluated. In a field-programmable gate array (FPGA), a feedback structure for polarization rotation speed detection and FIR coefficients update can be built up. In this feedback structure, the update coefficient of the filter will be adjusted to an optimal value with the change of detection result. The experimental results show that the establishment of this feedback structure improves the polarization tracking ability in the real-time coherent optical receiver.

关键词： Polarization tracking state of polarization finite impulse response field programmable gate array

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Kernel Normalised Least Mean Squares with Delayed Model Adaptation

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2020年第2期13卷 7-7页

作者： Fraser, Nicholas J. Leong, Philip H. W. Univ Sydney Sch Elect & Informat Engn Sydney NSW 2006 Australia

Kernel adaptive filters (KAFs) are non-linear filters which can adapt temporally and have the additional benefit of being computationally efficient through use of the "kernel trick". In a number of real-world applications, such as channel equalisation, the non-linear mapping provides significant improvements over conventional linear techniques such as the least mean squares (LMS) and recursive least squares (RLS) algorithms. Prior works have focused mainly on the theory and accuracy of KAFs, with little research on their implementations. This article proposes several variants of algorithms based on the kernel normalised least mean squares (KNLMS) algorithm which utilise a delayed model update to minimise dependencies. Subsequently, this work proposes corresponding hardware architectures which utilise this delayed model update to achieve high sample rates and low latency while also providing high modelling accuracy. The resultant delayed KNLMS (DKNLMS) algorithms can achieve clock rates up to 12x higher than the standard KNLMS algorithm, with minimal impact on accuracy and stability. A system implementation achieves 250 GOps/s and a throughput of 187.4 MHz on an Ultra96 board with 1.8x higher throughput than previous state of the art.

关键词： Kernel adaptive filters kernel normalised least mean squares field programmable gate array

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An Efficient and High-Speed Implementation of QRD-MGS Algorithm for STAP Application Based on Floating Point FPGAs

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2020年第3期29卷

作者： Hasanikhah, Narjes Amin-Nejad, Siavash Darvish, Ghafar Moniri, M. R. Islamic Azad Univ Sci & Res Branch Dept Elect & Comp Engn Tehran *** Iran Univ Guilan Dept Elect Engn Rasht *** Iran Islamic Azad Univ Yadegar E Emam Branch Dept Elect Engn Tehran *** Iran

Space-Time Adaptive Processing (STAP) can harness the efficacy of interference and clutter significantly. Calculations of the STAP weights involve solving linear equations which require very intensive computations. In this paper, the QR decomposition (QRD) using the modified gram-schmidt (MGS) algorithm is parameterized with vector size to create a trade-off between the hardware resources utilization and computation time. To achieve an efficient floating point structure, the proposed architecture of QRD-MGS algorithm is simulated and implemented in two modes: single-vector and multi-vector. Results show that the multi-vector method can lead to a high-performance design with higher operating frequency, lower power consumption, and less resource utilization than the single-vector method. For example, Modelism simulations show that the decomposition of a 12x51 matrix with vector size of 17 takes 7.86 mu s with the maximum clock frequency of 282MHz, for implementation on the Arria10 FPGA. In real STAP applications, the matrix sizes are too large to be fit on FPGAs and the update rate of the weights are high. Therefore, this method can fit any matrix in the contemporary FPGAs with an acceptable update rate.

关键词： field programmable gate array implementation QR decomposition space-time adaptive processing

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