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Efficient FPGA Implementation of Multilayer Perceptron for Real-Time Human Activity Classification

IEEE ACCESS 2019年 7卷 26696-26706页

作者： Gaikwad, Nikhil B. Tiwari, Varun Keskar, Avinash Shivaprakash, N. C. Visvesvaraya Natl Inst Technol Nagpur 440010 Maharashtra India Indian Inst Sci Bengaluru 560012 India

The smartphone-based human activity recognition (HAR) systems are not capable to deliver high-end performance for challenging applications. We propose a dedicated hardware-based HAR system for smart military wearables, which uses a multilayer perceptron (MLP) algorithm to perform activity classification. To achieve the flexible and efficient hardware design, the inherent MLP architecture with parallel computation is implemented on FPGA. The system performance has been evaluated using the UCI human activity dataset with 7767 feature samples of 20 subjects. The three combinations of a dataset are trained, validated, and tested on ten different MLP models with distinct topologies. The MLP design with the 7-6-5 topology is finalized from the classification accuracy and cross entropy performance. The five versions of the final MLP design (7-6-5) with different data precision are implemented on FPGA. The analysis shows that the MLP designed with 16-bit fixed-point data precision is the most efficient MLP implementation in the context of classification accuracy, resource utilization, and power consumption. The proposed MLP design requires only 270 ns for classification and consumes 120 mW of power. The recognition accuracy and hardware results performance achieved are better than many of the recently reported works.

关键词： Human activity recognition multilayer perceptron smart military wearables classifier hardware implementation field programmable gate array

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Adaptive absolute SCORE algorithm for spectrum sensing in cognitive radio

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MICROPROCESSORS AND MICROSYSTEMS 2019年 69卷 43-53页

作者： Nareshkumar, Shanigarapu Bikshalu, Kalagadda Vidya Bharathi Inst Technol Elect & Commun Engn Warangal 506201 Telangana India Kakathiya Univ Elect & Commun Engn Warangal Telangana India

The Cognitive Radio (CR) is one of the significant technology to enhance the spectrum utilization efficiency. The Radio Frequency (RF) spectrum is the most valuable natural resource. Due to an increased usage of the cognitive radio, the sensing issues in spectrum are increasing day by day. The CR is emerging technologies that increase the effectiveness and efficiency of the spread spectrum communication. Generally, the spectrum sensing is based on the energy detection and cyclostationary feature detection. The energy detection is a fundamental basic spectrum sensing technique. However, it performs poorly under a low Signal-to-Noise Ratio (SNR) environment. The cyclostationary based sensing technique improves Primary Users (PUs) detection performance with the high complexity of implementation and hardware utilization. Traditional median and Finite Impulse Response (FIR) filters are utilized complex adder and multiplier, which requires large memory space to store the filter coefficients and more hardware utilization. Hence, these filters have computational complexity and more hardware utilization. To overcome above-mentioned problems, Adaptive Absolute SCORE (AA-SCORE) architecture is designed based on optimal FIR filter for further reducing the system complexity to enhance the spectrum utilization efficiency in CR. In this research, the FIR filter is designed by using Radix-8 and Carry Select Adder (CSLA) for reducing the filter complexity. The proposed method is named as AAS-R8-CSLA architecture. The AAS-R8-CSLA architecture was implemented in the field programmable gate array (FPGA) platform through Verilog code. In order to improve the spectrum utilization efficiency of CR by using AAS-R8-CSLA. The experimental outcome showed that the proposed AAS-R8-CSLA architecture has improved FPGA performance up to 2-3% compared to existing methods like MS and ACS architecture. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Adaptive absolute SCORE Cognitive radio Carry select adder Finite impulse response field programmable gate array

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Cellular Automata with Synthetic Image - A Secure Image Communication with Transform Domain

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DEFENCE SCIENCE JOURNAL 2019年第3期69卷 259-265页

作者： Sundararaman, R. Upadhyay, H. N. Sridevi, A. Sivaraman, R. Anand, V Srinivasan, T. Savithri, S. SASTRA Deemed Univ Thanjavur 613401 India DRDO Combat Vehicles Res & Dev Estab Chennai 600054 Tamil Nadu India

Image encryption has attained a great attention due to the necessity to safeguard confidential images. Digital documents, site images, battlefield photographs, etc. need a secure approach for sharing in an open channel. Hardware - software co-design is a better option for exploiting unique features to cipher the confidential images. Cellular automata (CA) and synthetic image influenced transform domain approach for image encryption is proposed in this paper. The digital image is initially divided into four subsections by applying integer wavelet transform. Confusion is accomplished on low - low section of the transformed image using CA rules 90 and 150. The first level of diffusion with consecutive XORing operation of image pixels is initiated by CA rule 42. A synthetic random key image is developed by extracting true random bits generated by Cyclone V field programmable gate array 5CSEMA5F31C6. This random image plays an important role in second level of diffusion. The proposed confusion and two level diffusion assisted image encryption approach has been validated through the entropy, correlation, histogram, number of pixels change rate, unified average change intensity, contrast and encryption quality analyses.

关键词： Image encryption Confusion Diffusion Cellular automata IWT Synthetic image field programmable gate array

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FPGA Implementation of Distance-Independent Symbol Timing Synchronization in IM/DD OFDM-PON

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IEEE ACCESS 2019年 7卷 173731-173737页

作者： Chen, Xiaoyi Gao, Mingyi Sha, Yanping Zhang, Ji Fang, Erxi Ren, Hongliang Soochow Univ Sch Elect & Informat Engn Suzhou Key Lab Adv Opt Commun Network Technol Suzhou 215006 Peoples R China Zhejiang Univ Technol Coll Informat Engn Hangzhou 310023 Peoples R China

Intensity modulation/direct detection (IM/DD) orthogonal frequency division multiplexing (OFDM) is very suitable for high-speed cost-sensitive passive optical network (PON) applications. However, real-time OFDM systems are sensitive to synchronization bias, and thus symbol timing synchronization (STS) becomes a critical issue. We proposed a proportional-sign cross-correlation (PS-CC) STS algorithm with the advantages of distance-independence and low resource utilization. In the proposed PS-CC STS algorithm, the sign operation is applied instead of the multiplication operation with high computational complexity to decrease the resource utilization and the characteristic of low resource utilization will drive its application in real-time systems. Meanwhile, we use field programmable gate array (FPGA) to design a baseband IM/DD OFDM receiver with pipeline structure and built a universal loop test system, which is applied to implement the proposed PS-CC STS algorithm and evaluate its performance. In the experiment of a 16-QAM OFDM-PON system, a 30-km fiber transmission only results in 1.98% ripple on the peak amplitude of correlation, which verifies the distance-independence of the proposed method.

关键词： Orthogonal frequency division multiplexing symbol timing synchronization field programmable gate array

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A framework for high-level simulation and optimization of fine-grained reconfigurable architectures

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SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL 2019年第8期95卷 737-751页

作者： Pasha, Muhammad Adeel Farooq, Umer Siddiqui, Bilal LUMS Dept Elect Engn SBASSE Lahore Pakistan Dhofar Univ Elect & Comp Engn Dept Salalah Oman Purdue Univ Dept Elect & Comp Engn W Lafayette IN 47907 USA

field programmable gate arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.

关键词： High-level simulation embedded systems reconfigurable architectures field programmable gate array

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Root Cause Analysis and Classification of Single Point Failures in Designs Applying Triple Modular Redundancy in SRAM FPGAs

Root Cause Analysis and Classification of Single Point Failu...

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作者： Swift, James D. Brigham Young University

学位级别：M.Sc.

Radiation effects encountered in space or aviation environments can affect the configuration bits in field programmable gate arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

关键词： Single Event Upset field programmable gate array Triple Modular Redundancy Reliability SEU FPGA TMR James D. Swift Thesis

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Error estimation and enhanced stiffness sensitivity in contact resonance force microscopy with a multiple arbitrary frequency lock-in amplifier (MAFLIA)

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MEASUREMENT SCIENCE AND TECHNOLOGY 2020年第11期31卷

作者： Flater, Erin E. Mugdha, Arya C. Gupta, Saurabh Hudson, William A. Fahrenkamp, Abbigail A. Killgore, Jason P. Wilson, Jesse W. Luther Coll Dept Phys Decorah IA 52101 USA Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80521 USA NIST Appl Chem & Mat Div Boulder CO 80305 USA Colorado State Univ Sch Biomed Engn Ft Collins CO 80521 USA

In contact resonance force microscopy and related dynamic atomic force microscopy methods, an accurate description of the real-time cantilever dynamics is essential to the mapping of local material properties, such as viscoelasticity, piezo response, and chemical composition. Stiffness and damping variations of the tip-sample contact result in variations in the cantilever's resonance frequency and quality factor as it scans a sample of interest. When measuring characteristics of the resonance, generally, there is a tradeoff between full spectral coverage, best obtained by sweeping the amplitude versus frequency response in the time or frequency domain, and high-speed information, obtained by observing the cantilever response at one or two discrete frequencies, that may be required to track a resonance frequency that changes spatially. Here, we introduce a new option for performing contact resonance force microscopy with a low-cost multifrequency lock-in amplifier system with up to eight simultaneous independent excitation and detection frequencies. We demonstrate how the multifrequency approach can measure contact resonance frequency, quality factor, amplitude, and phase during imaging, with high precision and error estimation, without the need for frequency-tracking feedback. We show, using a wood composite sample, that this multifrequency approach can determine resonance frequency and quality factor, and associated uncertainty. This ability to estimate uncertainty of resonance parameters is not possible with 1 and 2 frequency methods. We further utilize the multifrequency lock-in to develop a novel means of increasing the stiffness range for highly sensitive nanomechanical sensing by dividing the eight lock-in frequencies to monitor two or four simultaneous eigenmodes, each of which is optimized for sensitivity in a particular stiffness regime. Overall, we show how multifrequency lock-in amplifiers with observation frequency chosen to coincide with an expected eig

关键词： atomic force microscopy contact resonance force microscopy lock-in amplifier field programmable gate array multifrequency AFM digital signal processing

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An Efficient and High-Speed Implementation of QRD-MGS Algorithm for STAP Application Based on Floating Point FPGAs

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2020年第3期29卷

作者： Hasanikhah, Narjes Amin-Nejad, Siavash Darvish, Ghafar Moniri, M. R. Islamic Azad Univ Sci & Res Branch Dept Elect & Comp Engn Tehran *** Iran Univ Guilan Dept Elect Engn Rasht *** Iran Islamic Azad Univ Yadegar E Emam Branch Dept Elect Engn Tehran *** Iran

Space-Time Adaptive Processing (STAP) can harness the efficacy of interference and clutter significantly. Calculations of the STAP weights involve solving linear equations which require very intensive computations. In this paper, the QR decomposition (QRD) using the modified gram-schmidt (MGS) algorithm is parameterized with vector size to create a trade-off between the hardware resources utilization and computation time. To achieve an efficient floating point structure, the proposed architecture of QRD-MGS algorithm is simulated and implemented in two modes: single-vector and multi-vector. Results show that the multi-vector method can lead to a high-performance design with higher operating frequency, lower power consumption, and less resource utilization than the single-vector method. For example, Modelism simulations show that the decomposition of a 12x51 matrix with vector size of 17 takes 7.86 mu s with the maximum clock frequency of 282MHz, for implementation on the Arria10 FPGA. In real STAP applications, the matrix sizes are too large to be fit on FPGAs and the update rate of the weights are high. Therefore, this method can fit any matrix in the contemporary FPGAs with an acceptable update rate.

关键词： field programmable gate array implementation QR decomposition space-time adaptive processing

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An Optimized S-Box Circuit for High Speed AES Design with Enhanced PPRM Architecture to Secure Mammographic Images

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JOURNAL OF MEDICAL SYSTEMS 2019年第2期43卷 1-8页

作者： Manojkumar, T. Karthigaikumar, P. Ramachandran, Varatharajan Karpagam Coll Engn Dept Elect & Commun Engn Coimbatore 641032 Tamil Nadu India Sri Ramanujar Engn Coll Dept Elect & Commun Engn Kancheepuram 600126 Tamil Nadu India

In AES, the total time taken by the architecture while implementing in low power and high-speed circuit is the most important thing that to be considered. Also in AES, implementing S-Boxes consumes the major part of the total time consumed by the entire architecture. In this research paper, we propose a very low-power and high efficient S-Box circuit architecture: a multi-stage modified version of PPRM architecture over composite fields. In this modified S box design, only AND and Hazard transparent XOR gates are used. Because of this architecture dynamic hazards which form the main aspect of power consumption in S box gets eliminated. A low propagation delay of 4.58ns and occupies 120 slices in the xilinx FPGA device xc6vlx75t-3ff784, while the low propagation delay and slice area is 5.552ns and 120 respectively for the conventional PPRM architecture. This new proposed architecture is used to protect the mammographic images from being unauthorized access.

关键词： Advanced encryption standard Positive polarity reed muller S-Box Hazard field programmable gate array Application specific integrated circuits BDD SOP Data encryption standard Pipeline architecture Mammographic images

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Design and implementation of LTE physical layer on FPGA

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INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY 2019年第1-2期61卷 127-134页

作者： Venkataramanan, V. Lakshmi, S. Kanetkar, Vineet A. Sathyabama Inst Sci & Technol Sch Elect & Elect Engn Dept Elect & Commun Chennai 119 Tamil Nadu India Dwarakadas J Sanghvi Coll Engn Dept Elect & Telecommun Mumbai 56 Maharashtra India

Changing trends in the communication industry pertaining to configuration of devices and their processing for maximised result. Each device needs a processing unit comprising a microcontroller or a field programmable gate array (FPGA). This paper deals with the use of FPGAs and how they can be configured as Hardware in Loop (HIL) for validation along with Simulink and Xilinx System Generator (XSG). Further, their compatibility is mentioned for long term use and durability in communication. The comparison of related work in the field of communication is done with the FPGA implementation of Long Term Evolution (LTE) physical layer with different modulation schemes, different antenna configurations and different signal to noise ratio systems implemented on Virtex and Spartan FPGA boards. On the other hand the simulation is carried out with Xilinx Vivado Design suite to analyse the power, resource utilisation, timing summary and memory utilisation.

关键词： field programmable gate array hardware co-simulation LTE MIMO OFDM 3GPP

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