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检索条件"主题词=Field Programmable Gate array"

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Towards a Heterogeneous Fault-Tolerance Architecture based on Arm and RISC-V Processors 45

Towards a Heterogeneous Fault-Tolerance Architecture based o...

引用

45th Annual Conference of the IEEE Industrial Electronics Society (IECON)

作者： Rodrigues, Cristiano Marques, Ivo Pinto, Sandro Gomes, Tiago Tavares, Adriano Univ Minho Ctr ALGORITMI Braga Portugal

ISBN: (纸本)9781728148786

Computer systems are permanently present in our daily basis in a wide range of applications. In systems with mixed-criticality requirements, e.g., autonomous driving or aerospace applications, devices are expected to continue operating properly even in the event of a failure. An approach to improve the robustness of the device's operation lies in enabling faulttolerant mechanisms during the system's design. This article proposes Lock-V, a heterogeneous architecture that explores a Dual-Core Lockstep (DCLS) fault-tolerance technique in two different processing units: a hard-core Arm Cortex-A9 and a softcore RISC-V-based processor. It resorts a System-on-Chip (SoC) solution with software programmability (available trough the hard-core Arm Cortex-A9) and field-programmable gate array (FPGA) technology, taking advantages from the latter to support the deployment of the RISC-V soft-core along with dedicated hardware accelerators towards the realization of the DCLS.

关键词： Dual-core lockstep fault tolerance heterogeneous architectures field programmable gate array RISC-V Arm

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A 10 MSample/Sec Digital Neural Spike Detection for a 1024 Pixels Multi Transistor array Sensor 26

A 10 MSample/Sec Digital Neural Spike Detection for a 1024 P...

引用

26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Tambaro, M. Vallicelli, E. A. Tomasella, D. Baschirotto, A. Vassanelli, S. Maschietto, M. De Matteis, M. Univ Milano Bicocca Dept Phys Milan Italy Univ Padua Dept Biomed Sci Padua Italy

ISBN: (纸本)9781728109961

This paper presents an FPGA implementation of a DSP performing real time spike detection on the electrical activity of an in vitro neuronal culture of rat hippocampi. The DSP enhances the Signal-to-noise ratio (SNR) of samples recorded by a 1024 pixels Multi Transistor array (MTA) at 9375 Samples/Sec per pixel of similar to 6 mu m pitch. The implementation integrates in the same system a Time Division Multiplexing (TDM) filter and a spatio-temporal correlation algorithm, to increase the SNR up to identify spikes as low as 215 mu V0-PEAK. The digital filter is a 2nd order high pass Infinite input response (IIR) Chebyshev filter. The spatio-temporal correlation exploits the MTA smaller pixels size and the high sample-rate to compute an equivalent pixel from a group of 7 pixels and 3 consecutive frames for a total of 21 samples and it is supported by a multi-channel noise power estimation. Finally, this paper shows the results achieved on the performed experiments and compares the system with others experiments using different sensors and algorithms.

关键词： Real-Time Systems field programmable gate array Neuroscience Digital signal processing

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Active Stereo Vision with High Resolution on an FPGA 27

Active Stereo Vision with High Resolution on an FPGA

引用

27th IEEE Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Pfeifer, Marc Scholl, Philipp M. Voigt, Rainer Becker, Bernd Univ Freiburg Chair Comp Architecture Freiburg Germany Ensenso GmbH Freiburg Germany

ISBN: (纸本)9781728111315

We present a novel FPGA based active stereo vision system, tailored for the use in a mobile 3D stereo camera. For the generation of a single 3D map the matching algorithm is based on a correlation approach, where multiple stereo image pairs instead of a single one are processed to guarantee an improved depth resolution. To efficiently handle the large amounts of incoming image data we adapt the algorithm to the underlying FPGA structures, e.g. by making use of pipelining and parallelization. Experiments demonstrate that our approach provides high-quality 3D maps at least three times more energy-efficient (5.5 fps/W) than comparable approaches executed on CPU and GPU platforms. Implemented on a Xilinx Zynq-7030 SoC our system provides a computation speed of 12.2 fps, at a resolution of 1.3 megapixel and a 128 pixel disparity search space. As such it outperforms the currently best passive stereo systems of the Middlebury Stereo Evaluation in terms of speed and accuracy. The presented approach is therefore well suited for mobile applications, that require a highly accurate and energy-efficient active stereo vision system.

关键词： field programmable gate array stereo vision stereo correlation parallelization pipelining depth information hardware

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Behavior of a Hippocampal Spiking Network and FPGA Implementation 38

Behavior of a Hippocampal Spiking Network and FPGA Implement...

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38th Chinese Control Conference (CCC)

作者： Hao, Jingyi Hao, Xinyu Wang, Jiang Yang, Shuangming Deng, Bin Yu, Haitao Tianjin Univ Sch Elect & Informat Engn Tianjin 300072 Peoples R China

ISBN: (纸本)9789881563972

The hippocampus in human brain is responsible for memory processing and tasks learning, which has long been one of the main interests of many researchers. In this paper, a spiking neural network of the hippocampus is realized based on a designed task. In the task, the model rat firstly gets familiar with the environment and finds item in one of the pots and finally gets a reward for making the correct response. Through the network, the feature of the hippocampal neurons can be simulated in software successfully. The three-layer network was built based on the spike-timing dependent synaptic plasticity and the synaptic weights will be modified between layers during task which can finally achieve the memory-related behavior of the model rat. Besides software realization, we also utilize field programmable gate array (FPGA) to reproduce the characteristics of the network in real time. The results show that the spiking neural network of the hippocampus can mimic the memory-related behavior of the model rat.

关键词： Hippocampus spiking neural network memory-related behavior field programmable gate array

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A Fast Blink-Control System Based on FPGA 2

A Fast Blink-Control System Based on FPGA

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2nd International Conference on Image and Video Processing, and Artificial Intelligence (IPVAI)

作者： Cai, Siwen Wang, Peng Zhang, Qiang Chen, Yuanyuan Harbin Univ Sci & Technol Sch Elect & Elect Engn Harbin 150080 Peoples R China

ISBN: (数字)9781510634107

ISBN: (纸本)9781510634107

People have been pursuing fast and convenient methods to control machines. However, the existing human-computer interaction methods still have many shortcomings. We present here a fast blink-control system based on FPGA. The video image processing technologies were utilized to realize the blink-control algorithm and the Verilog hardware description language (Verilog HDL) was taken to develop functional modules on the FPGA. Positioning human eye and recognizing blink were implemented with integral projection method based on gradient operator according to features of eyes. Then, subsequent operations were performed based on judgement results. The designed fast blink-control system was verified on ALTER FPGA development platform. The results showed that the accuracy to detect eye blink (front face, no inclination) was 98% and the average response time of the system was about 413ms, which reached the real-time detection level. Therefore, it has achieved the goal to provide a new control mode which is fast and effective.

关键词： blink control field programmable gate array human eyes positioning video processing intelligent control

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FPGA-Accelerated Multispectral Ultra-High Resolution SAR-Imaging with Wideband FMCW Radars

FPGA-Accelerated Multispectral Ultra-High Resolution SAR-Ima...

引用

IEEE Radio and Wireless Symposium (RWS)

作者： Siska, Jan Jaeschke, Timo Wagner, Jonas Pohl, Nils Ruhr Univ Bochum D-44801 Bochum Germany

ISBN: (纸本)9781538659441

An energy efficient stand-alone SAR-system based on the global backprojection algorithm using FPGA acceleration is presented. Three different radar sensors with very wide bandwidths operating at 80 GHz, 144 GHz and 240 GHz are simultaneously connected to the processor. A hardware accelerator is implemented using a systolic array architecture via high-level synthesis. As system platform, a Xilinx Zynq Ultrascale+ system on a chip (SoC) was used. A speedup of 177 was achieved with an optimized hardware architecture in comparison to a software solution running on the integrated ARM A53 quadcore. The system allows for measuring and focusing multiple high-resolution images in less than 20 seconds.

关键词： Synthetic aperture radar millimeter wave radar field programmable gate array backprojection

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Modification of Initialization Vector for Parallel CMAC Algorithm 10

Modification of Initialization Vector for Parallel CMAC Algo...

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10th IEEE International Conference on Software Engineering and Service Science (ICSESS)

作者： Pirzada, Syed Jahanzeb Hussain Murtaza, Abid Shahid, Muhammad Xu, Tongge Liu Jianwei Beihang Univ Sch Cyber Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781728109459

The growing number of threats and attacks on communication systems has encouraged researchers to identify methods for providing security for data communication. Besides the encryption and authentication algorithms provide data security services for communication systems. However, the recent attacks on communication systems reveal that the attacks utilize the analysis of plaintext/ciphertext to breach the security of communication systems. Therefore, the plaintext should be randomized to prevent correlation between ciphertext. In this work, an algorithm is proposed for increasing ciphertext randomness in Parallel Cipher-based Message Authentication Code (PCMAC) Algorithm. The proposed algorithm utilizes the high throughput of PCMAC authenticated encryption algorithm for providing high throughput and more randomized ciphertext. The proposed algorithm is implemented for generation of Initialization Vector (IV) using the GEFFE generator and right shift operation for creating randomness in the ciphertext. The comparisons result show that the proposed implementation is more randomized as compared to the previous implementation.

关键词： Advanced Enctyption Standard field programmable gate array Initialization Vector Parallel Cipher-hosed Message Authentication Code

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Implementation of Digital Lock-in Amplifier Based on High-level Synthesis 4

Implementation of Digital Lock-in Amplifier Based on High-le...

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4th IEEE International Conference on Signal and Image Processing (ICSIP)

作者： Huang, Kan Zhang, Xibin Chen, Dihu Cai, Zhigang Wang, Zixin Wang, Min Sun Yat Sen Univ Sch Elect & Informat Technol Guangzhou Peoples R China Chinese Acad Sci Guangzhou Inst Geochem Guangzhou Peoples R China

ISBN: (纸本)9781728136608

Recently, digital lock-in amplifiers (DLIAs) have been widely used in scientific research field for measuring weak signals. The method of implementing a DLIA hardware (like field programmable gate array) from the high-level specifications (such as C or C++) is required for software engineers. High-level synthesis (HLS) tool enables the realization of hardware design from high-level specifications automatically. The implementation of the DLIA by HLS is introduced in detail in this paper. The simulation results verify the feasibility of the implementation of the DLIA by HLS.

关键词： Digital Lock-in Amplifier high-level synthesis field programmable gate array

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Impact of Intentional Electromagnetic Interference on Pure Combinational Logic

Impact of Intentional Electromagnetic Interference on Pure C...

引用

International Symposium on Electromagnetic Compatibility (EMC EUROPE)

作者： Trabelsi, Oualid Sauvage, Laurent Danger, Jean-Luc Inst Polytech Paris Saclay Telecom ParisTech LTCI Gif Sur Yvette France

ISBN: (纸本)9781728105932

Electromagnetic fault injection is a growing topic when it is applied to jeopardize the security of integrated circuit. Indeed, if the main part of the process will focus on the hardware efficiency of the near-field probes, tweaking properties of the electromagnetic disturbance can also lead to the success of the attack. In this paper, we are presenting characterization results of intentional electromagnetic interference by measuring its impact within the target, and more precisely on the propagation delay of a combinational logic path. The evaluation of the impact shows that the electromagnetic coupling between the probe and the integrated circuit strongly depends on the characterized properties.

关键词： Side-channel attacks immunity testing probes field programmable gate array

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Hardware Implementation of A Synthetic Inertia System for Grid Stability 8

Hardware Implementation of A Synthetic Inertia System for Gr...

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International Conference on Renewable Energy Research and Applications

作者： Fregelius, Martin Lundin, Urban Uppsala Univ Div Elect Dept Engn Sci Box 534 SE-75121 Uppsala Sweden

ISBN: (纸本)9781728135878

The frequency in the electrical grid is, on the short time-scale, stabilized by the total rotational mass given predominantly by synchronously connected devices. These devices include the generators themselves and, on slightly longer timescales, the control system acting on turbine governors. As the inverter-connected technologies increase their share of total power, the total inertia in the grid is significantly reduced. One way to stabilize the frequency and reduce low frequency oscillations is to add synthetic inertia provided by a small energy, high power, storage devices combined with a fast control system. This paper describes a possible hardware topology for linear synthetic inertia. It uses an inverter coupled to a local energy storage unit comprised of supercapacitors. The paper presents the implementation and some selected experimental results. The system response is fast enough on a small test grid to act as inertia.

关键词： Synthetic inertia Three phase inverter Super capacitors field programmable gate array distributed generation Grid tied energy storage

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