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检索条件"主题词=Field Programmable Gate array"

共 1340 条记录，以下是481-490 订阅

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Real-Time Neural (RT-Neu) Spikes Imaging by a 9375 sample/(sec pixel) 32x32 pixels Electrolyte-Oxide-Semiconductor Biosensor 15

Real-Time Neural (RT-Neu) Spikes Imaging by a 9375 sample/(s...

引用

15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

作者： Tambaro, M. Vallicelli, E. A. Tomasella, D. Baschirotto, A. Vassanelli, S. Maschietto, M. De Matteis, M. Univ Milano Bicocca Dept Phys Milan Italy Univ Padua Dept Biomed Sci Padua Italy

ISBN: (纸本)9781728135496

This paper presents a Real-Time Neural Spikes (RT-Neu) Imaging system on FPGA that processes and detects the electrical activity of a neurons population taken from rat hippocampi on an Electrolyte-Oxide-Semiconductor (EOS) Multi Electrode array (MEA) local matrix of 32x32 pixels. RT-Neu has been implemented on Xilinx Zynq-7000 ARM/FPGA SoC. It receives the neural signals coming from a 9.375 kSample/(***) 32x32 pixels EOS Biosensor, filters the single-pixel low-frequency offset/noise components and finally performs a multi-pixel signal processing (using a PCA-based correlation algorithm) to provide a final spatial map of the neural culture electrical activity. The correlation algorithm has been implemented to operate on multiplexed signals allowing to identify single neural Action Potentials (AP) with amplitudes as low as 215 mu V0-PEAK. A dedicated GUI has been developed to monitor in real- time the neuron population electrical activity and whose demo video can be found at [1].

关键词： Biological neural networks Real-Time Systems field programmable gate array Neuroscience Digital signal processing

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Optimization of Signal Processing Chains: Application to Cascaded Filters 27

Optimization of Signal Processing Chains: Application to Cas...

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27th European Signal Processing Conference (EUSIPCO)

作者： Hugeat, A. Bernard, J. Friedt, J-M Bourgeois, P-Y Goavec-Merou, G. Univ Bourgogne Franche Comte FEMTO ST Inst CNRS Besancon France

ISBN: (纸本)9789082797039

The design of digital signal processing chains must meet competing requirements by maximizing performance (e.g. rejection in the case of a filter) while reducing resource consumption. In this paper, we explore a new methodology for designing chains assembled by cascading basic processing blocks. We apply this optimization strategy to the example of a cascade of Finite Impulse Response (FIR) filters. While the design of cascaded FIR filters generally focuses on low-level details, we provide a high-level model. This development strategy can be generalized for any signal processing chain made by assembling blocks whose resource consumption is qualified: a solver aims at meeting multiple objectives including minimizing resource consumption or optimizing performance. This result is then transformed into a synthesizable solution targeting a reconfigurable field programmable gate array (FPGA). The experiments show that this approach gives efficient results, both on the quality of the signal filtering and the processing resource used for the design.

关键词： field programmable gate array Finite Impulse Response filter Optimization

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Acceleration and Implementation of Convolutional Neural Network Based on FPGA 7

Acceleration and Implementation of Convolutional Neural Netw...

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7th IEEE International Conference on Computer Science and Network Technology (ICCSNT)

作者： Wang, Enyi Qiu, Dehui Capital Normal Univ Informat & Engn Coll Beijing Peoples R China

ISBN: (纸本)9781728132990

Aiming at the problem of high power consumption and slow operation speed of neural network in embedded system, this paper presents an automatic design method of convolutional neural network (CNN) accelerator based on field programmable gate array (FPGA) to meet the requirements of embedded terminal for operation performance and power consumption. Firstly, in order to reduce the storage resources of the FPGA and the time required for network computing, the weight quantization method is used to convert network parameters from floating-point data to binary data. Secondly, in order to improve the speed and throughput of the whole system, coarse-grained and fine-grained parallel computing optimization methods are used. In this paper, the above acceleration scheme will be applied to the scene of unmanned aerial vehicle (UAV) object detection. The test results shows that the power consumption of the system is 2.38W and the calculated power consumption ratio is 29.3GOPS/W. Compared with the work of related literature in recent years, the proposed scheme can provide higher speed and efficiency. The experimental results show that the accuracy of the IOU is 21% and the speed is 7FPS.

关键词： Convolutional Neural Network field programmable gate array Weight quantization Parallel computing Object detection

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Tile TDAQ interface module for the Phase-II Upgrade of the ATLAS Tile Calorimeter

Tile TDAQ interface module for the Phase-II Upgrade of the A...

引用

IEEE Nuclear Science Symposium / Medical Imaging Conference (NSS/MIC)

作者： Yue, Xiaoguang Heidelberg Univ Kirchhoff Inst Phys Neuenheimer Feld 227 D-69120 Heidelberg Germany

ISBN: (纸本)9781728141640

In order to meet the requirements for the High Luminosity-Large Hadron Collider (HL-LHC), a completely new architecture will be used to redesign the readout electronics of the ATLAS Tile Calorimeter (TileCal) system for the ATLAS Phase-II Upgrade. In the new Trigger and Data AcQuisition (TDAQ) architecture, the output signals of the Tile detector cells will be digitized in the front-end electronics and transferred for every bunch crossing to the off-detector Tile PreProcessor (TilePPr) modules through high-speed optical links. The TilePPr will then reconstruct energy deposited in each cell from the digitized samples and transfer the pre-processed cell energy data further to the Tile TDAQ interface (TileTDAQi) modules. The TileTDAQi will then group the cell energy data to generate trigger primitives with different granularity and implement interfaces based on different requirements from the Feature Extractor (FEX) and other trigger processor modules. At the same time, the TilePPr will also store the energy information in pipeline memories and send selected data out to the ATLAS data acquisition system through the TileTDAQi. The TileTDAQi module will be implemented on an Advanced Telecommunications Computing Architecture (ATCA) Rear Transition Module (RTM) format and will operate under the ATCA framework. In order to verify the basic functionality and interfaces of the TileTDAQi, a lightweight prototype has been designed and is now under test. This contribution will provide an overview of the new TileCal back-end electronics architecture and present the design and implementation of the TileTDAQi prototype together with preliminary test results.

关键词： High Energy Physics ATLAS Tile Calorimeter DAQ system field programmable gate array ATCA

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An Optimized FPGA Implementation of DCT Architecture for Image and Video Processing Applications

An Optimized FPGA Implementation of DCT Architecture for Ima...

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4th IEEE International Conference on Wireless Communications Signal Processing and Networking (WiSPNET) - Advancing Wireless and Mobile Communications Technologies for 2020 Information Society

作者： Pari, J. Britto Vaithiyanathan, D. Sri Sairam Engn Coll Dept Elect & Commun Engn Chennai Tamil Nadu India Natl Inst Technol Dept Elect & Commun Engn Delhi India

ISBN: (数字)9781538692790

ISBN: (纸本)9781538692790

The development of portable devices such as digital cameras and mobile phones led to higher amount of research being dedicated to image and video processing systems. In particular, video processing coding technique such as High Efficiency Video Coding (HEVC) requires low power consumption for the multimedia applications, this leads to extensive development in low area and high speed algorithms. The log time Discrete Cosine Transform (DCT) is increasingly employed for compression standards, since it has remarkable energy compaction properties. Pipelined and MAC based DCT have been implemented in digital hardware to offer better compression at very low circuit complexity. In this paper, a Time division multiplexing (TDM) based DCT architecture is implemented using the concept of resource sharing principle which possess low computational complexity and high speed. This hardware implementation results in reduced area and increased speed compared to the conventional DCT architectures implemented in field programmable gate array (FPGA) devices.

关键词： Discrete Cosine Transform Video coding Pipelined MAC Time Division Multiplexing field programmable gate array

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Zero Knowledge Authentication for Reuse of IPs in Reconfigurable Platforms

Zero Knowledge Authentication for Reuse of IPs in Reconfigur...

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IEEE Region 10 Conference on Technology, Knowledge, and Society (TENCON)

作者： Guha, Krishnendu Saha, Debasri Chakrabarti, Amlan Univ Calcutta AK Choudhury Sch Informat Technol Kolkata India

ISBN: (纸本)9781728118956

A key challenge of the embedded era is to ensure trust in reuse of intellectual properties (IPs), which facilitates reduction of design cost and meeting of stringent marketing deadlines. Determining source of the IPs or their authenticity is a key metric to facilitate safe reuse of IPs. Though physical unclonable functions solves this problem for application specific integrated circuit (ASIC) IPs, authentication strategies for reconfigurable IPs (RIPs) or IPs of reconfigurable hardware platforms like field programmable gate arrays (FPGAs) are still in their infancy. Existing authentication techniques for RIPs that relies on verification of proof of authentication (PoA) mark embedded in the RIP by the RIP producers, leak useful clues about the PoA mark. This results in replication and implantation of the PoA mark in fake RIPs. This not only causes loss to authorized second hand RIP users, but also poses risk to the reputation of the RIP producers. We propose a zero knowledge authentication strategy for safe reusing of RIPs. The PoA of an RIP producer is kept secret and verification is carried out based on traversal times from the initial point to several intermediate points of the embedded PoA when the RIPs configure an FPGA. Such delays are user specific and cannot be replicated as these depend on intrinsic properties of the base semiconductor material of the FPGA, which is unique and never same as that of another FPGA. Experimental results validate our proposed mechanism. High strength even for low overhead ISCAS benchmarks, considered as PoA for experimentation depict the prospects of our proposed methodology.

关键词： Authentication Zero Knowledge Proof Intellectual Property field programmable gate array

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Optically Reconfigurable gate array with a Triple Modular Redundancy 6

Optically Reconfigurable Gate Array with a Triple Modular Re...

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6th International Conference on Space Science and Communication (IconSpace) - Advancing Space Science for Societal Sustainability

作者： Yoshinaga, Toru Watanabe, Minoru Shizuoka Univ Grad Sch Integrated Sci & Technol 3-5-1 Johoku Hamamatsu Shizuoka 4328561 Japan

ISBN: (纸本)9781538683941

Space systems require radiation-hardened devices with high soft-error tolerance and high total-ionizing-dose tolerance. An optically reconfigurable gate array (ORGA) with over 400 Mrad total-ionizing-dose has been developed. The total-ionizing-dose tolerance of the ORGA is 400 times higher than currently available radiation-hardened devices. Moreover, the ORGAs can support high-speed scrubbing of configuration memory so that soft errors on configuration memory can be ignored during operations. However, soft-errors that arise on the programmable gate array side must be removed. Therefore, this paper presents a new ORGA VLSI with a triple modular redundancy gate array structure that can completely remove soft-errors on its programmable gate array.

关键词： field programmable gate array Optically reconfigurable gate array Total-ionizing-dose tolerance Triple modular redundancy

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Image and Video Processing Applications Using Xilinx System Generator 7

Image and Video Processing Applications Using Xilinx System ...

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7th International Symposium on Digital Forensics and Security (ISDFS)

作者： Yaman, Sertac Yildirim, Merve Kamislioglu, Bircan Erol, Yavuz Kurum, Hasan Firat Univ Dept Elect & Elect Engn Elazig Turkey

ISBN: (纸本)9781728128276

This paper presents some image and video processing applications by using Xilinx System Generator ( XSG) to implement into field programmable gate array (FPGA). All algorithms which are gray conversion, inversion, enhancement, erosion and dilation, thresholding, and edge detection are included in this study. These methods are generally applied on an image or a video in the literature. Differently in this study, the algorithms are applied on an image and the video. Besides, the edges of the objects in a video are also detected by utilizing these methods. The design is verified and validated by using XSG at Matlab/Simulink to implement into the FPGA.

关键词： field programmable gate array image processing Matlab/Simulink video processing Xilinx System Generator

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An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor 18

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Proce...

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International Conference on field-programmable Technology (ICFPT)

作者： Mashimo, Susumu Fujita, Akifumi Matsuo, Reoma Akaki, Seiya Fukuda, Akifumi Koizumi, Toru Kadomoto, Junichiro Irie, Hidetsugu Goshima, Masahiro Inoue, Koji Shioya, Ryota Kyushu Univ Fukuoka Japan Univ Tokyo Tokyo Japan Nagoya Univ Nagoya Aichi Japan Natl Inst Informat Tokyo Japan

ISBN: (纸本)9781728129433

High-performance soft processors in field-programmable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack. An out-of-order (000) superscalar approach is a good candidate to improve performance in such cases, as evidenced from OoO hard processor studies. Recent studies have revealed, however, that conventional OoO processor components do not fit well in an FPGA, and it is thus important to carefully design such components for FPGA characteristics. Hence, we propose the RSD processor: a new, open-source OoO RISC -V soft processor optimized for an FPGA. The RSD supports many aggressive OoO execution features, like speculative scheduling, OoO memory instruction execution and disambiguation, a memory dependence predictor, and a non-blocking cache. While the RSD supports such aggressive features, it also leverages FPGA characteristics. Therefore, it consumes fewer FPGA resources than are consumed by existing OoO soft processors, which do not support such aggressive features well. We first introduce the end result of the RSD microarchitecture design and then describe several novel optimization techniques. The RSD achieves up to 2.5-times higher Dhrystone MIPS while using 60% fewer registers and 64% fewer lookup tables (LUTs) as compared to state-of-the-art, open-source OoO processors.

关键词： field programmable gate array Multi port RAM Open source Out of order processor RISC V Soft processor

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FPGA-based Design and Implementation of Real-time Robot Motion Planning 9

FPGA-based Design and Implementation of Real-time Robot Moti...

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9th International Conference on Information Science and Technology (ICIST)

作者： Li, Ruige Huang, Xiangcai Tian, Sijia Hu, Rong He, Dingxin Gu, Qiang Huazhong Univ Sci & Technol Wuhan Peoples R China PS Micro Wuhan Peoples R China

ISBN: (纸本)9781728121062

Collision detection in motion planning is time-consuming for robotic arm applications, especially real-time motion planning in a dynamic environment. It is necessary to design a collision detection accelerator for real-time robot motion planning. In this paper, an optimized FPGA-based design is proposed to reduce the hardware cost. Static random access memory (SRAM) is used to store encoded collision detection data for saving the FPGA look up tables (LUTs). The collision detection accelerator implementations based on SRAM and LUT are analyzed and compared in terms of hardware cost and time consumption. Experimental results are shown to prove the efficiency of the proposed design and implementation.

关键词： motion planning collision detection field programmable gate array accelerator static random access memory

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