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International Conference on Computer Communication and Informatics (ICCCI)

作者： Aswini Chinthala, Ramesh Murty, N. S. Amrita Vishwa Vidyapeetham Amrita Sch Engn Dept Elect & Commun Engn Bengaluru 560035 India

ISBN: (纸本)9781538682593

Modern FPGA families have inbuilt, fast and dedicated carry chain logic embedded in the configurable logic blocks which improves the performance of adder circuitry. In this paper we propose a fast and area efficient adder for Xilinx FPGA families by efficiently utilizing the 6-input LUTs and inbuilt dedicated carry logic chain. The proposed adder is implemented by splitting the N-bit adder into three sections where the first section consists of K/2 carry compression (cc) cells which calculates the carry of K least significant bits and this carry out is given as the carry input to calculate the sum of M most significant bits. The second section consists of K/2 sum-out (so) cells which calculates the sum of k least significant bits and the third section consists of M carry select adder (csa) cells instead of M ripple carry adder for calculating the sum of M most significant bits which in turn reduces the delay without any increase in area. The result shows that the proposed adder architecture with carry select adder and carry chain is faster than the one with normal ripple carry adder without any area overhead. The proposed N-bit adder improves the delay by about 16% (32-bit) to 29% (128-bit) compared to the state-of-the-art N-bit adder [8] and a normal adder respectively.

关键词： field programmable gate array Carry Select Adder LUT Carry chain Delay Area

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Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation 22

Improving Digital Circuit Simulation with Batch-Parallel Log...

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45th Euromicro Conference on Software Engineering and Advanced Applications (SEAA) / 22nd Euromicro Conference on Digital System Design (DSD)

作者： Patrou, Maria Legault, Jean-Philippe Graham, Aaron G. Kent, Kenneth B. Univ New Brunswick Fac Comp Sci Fredericton NB Canada

ISBN: (纸本)9781728128610

Integrated circuit simulators reproduce the behavior and functionality of the underlying circuits. They are part of FPGA CAD flow tools and they ensure the correctness of the circuits after the various conversions and optimizations occurring in the previous stages. During this procedure a graph with dependencies across nodes is created for each circuit design. Large circuits, and thus graphs, require more time to be simulated, making a parallel approach necessary. We explore a new solution-batch-parallel simulation in which the circuit output is calculated by worker threads that process batches of input vectors. The threads traverse and calculate their assigned nodes in parallel taking into consideration the intra-node dependencies. Furthermore, a node calculation analysis is performed and used to achieve work balance across threads. We apply this technique on the open-source Odin II framework and compare it with the existing approaches. The batch-parallel simulation is compared with the two existing approaches, single-threaded and multi-threaded, under various configurations, considering the number of threads and the batch sizes. The results demonstrate performance gains against the existing approaches in the majority of the benchmarks used for specific metrics, such as simulation elapsed time.

关键词： field programmable gate array FPGA VTR CAD flow ODIN II parallel batch simulation

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A Hardware Implementation of Craik-O' Brien Effect-Based Contrast Improvement for Dichromats

A Hardware Implementation of Craik-O' Brien Effect-Based Con...

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International Forum on Medical Imaging in Asia

作者： Ono, Tomohiro Kubota, Ryosuke Suetake, Noriaki Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan Natl Inst Technol Ube Coll Dept Intelligent Syst Engn Ube Yamaguchi Japan Yamaguchi Univ Grad Sch Sci & Technol Innovat Yamaguchi Japan 2-4 Hibikino Kitakyushu Fukuoka 8080196 Japan

ISBN: (数字)9781510627765

ISBN: (纸本)9781510627765

In this study, we designed a digital hardware circuit for a field-programmable gate array (FPGA) to provide an effective contrast improvement algorithm for dichromats. The proposed method employs the Craik-O Brien (C-O) effect. The C-O effect is an optical illusion effect in which subjective contrast is created from contour information. In the proposed method, the contrast modification is only conducted around the contours of objects to apply the C-O effect for dichromats. To extract the contour information of objects, a T-model filter which only requires a one-line buffer is introduced. The proposed method can realize the C-O effect without using dividers and multipliers. Therefore, it is relatively simple to implement in the FPGA. Through experiments with software and logic simulation, the effectiveness and validity of the proposed method were evaluated.

关键词： Dichromats Image processing Craik-O' Brien effect T-model filter Digital hardware field programmable gate array

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SEQUENTIAL PEAK DETECTION FOR FLOW CYTOMETRY 27

SEQUENTIAL PEAK DETECTION FOR FLOW CYTOMETRY

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27th European Signal Processing Conference (EUSIPCO)

作者： Guel, Goekhan Alebrand, Sabine Bassler, Michael Wittek, Joern Fraunhofer Inst Microengn & Microsyst IMM Carl Zeiss Str 18-20 D-55129 Mainz Germany

ISBN: (纸本)9789082797039

Circulating tumor cells in blood are identified by means of sequential peak detection taking into account the memory and real time applicability constraints. Three different spatial domain algorithms: derivative approach, energy detector and baseline method are compared with three different peak detection algorithms based on machine learning: linear and nonlinear support vector machines and artificial neural networks. Performance of the peak detection algorithms are tested on both synthetic and real data. Experimental results indicate superiority of machine learning algorithms over the other three algorithms which are widely used in practice. Due to Gaussianity assumption in the signal model, a linear support vector machine is found to be as good as other machine learning schemes.

关键词： Peak detection flow cytometry machine learning classification filtering field programmable gate array

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Simulation of Man in the Middle Attack On Smart Grid Testbed

Simulation of Man in the Middle Attack On Smart Grid Testbed

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IEEE SoutheastCon Conference

作者： Fritz, Jared J. Sagisi, Joseph James, John St Leger, Aaron King, Kyle Duncan, Kate J. US Mil Acad Elect Engn & Comp Sci West Point NY 10996 USA

ISBN: (纸本)9781728101378

Over the past decade, the frequency of cyber attacks against power grids has steadily increased, requiring researchers to find and patch vulnerabilities before they can be exploited. Our research introduces the prototype of a man-in-the-middle attack to be implemented on a microgrid emulator of a smart grid. We present a method of violating the integrity and authentication of packets that are using the IEEE Synchrophasor Protocol in a controlled environment, but this same approach could be used on any other protocol that lacks the proper overhead to ensure the integrity and authenticity of packets. In future research, we plan to implement and test the attack on the previously mentioned smart grid testbed in order to assess the attacks feasibility and tangible effects on Wide Area Monitoring and Control applications, as well as propose possible countermeasures. For this paper, we developed a working simulation of our intended attack using the software ModelSim 10.4. The attack will modify network packet data coming from a Schweitzer Engineering Labs (SEL) Phasor Measurement Unit (PMU) hardware sensor, which provides a stream of precise timing values associated with current and voltage values, as these measured values are en route to the Open Phasor Data Concentrator (OpenPDC) application running on a Windows server. Our simulation provides and validates all of the necessary code in order to program a field programmable gate array and execute our attack on the testbed in future research.

关键词： Man-in-the-Middle Attacks Phasor Measurement Unit Security Smart Grid Supervisory Control and Data Acquisition field programmable gate array

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Coding Techniques in Verilog for Finite State Machine Designs in FPGA 18th

Coding Techniques in Verilog for Finite State Machine Design...

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18th International Conference on Computer Information Systems and Industrial Management

作者： Salauyou, Valery Zabrocki, Lukasz Bialystok Tech Univ Fac Comp Sci Bialystok Poland

ISBN: (纸本)9783030289560;9783030289577

Coding techniques in Verilog HDL of finite state machines (FSMs) for synthesis in field programmable gate arrays (FPGAs) are researched, and the choice problem the best FSM coding styles in terms of an implementation cost (area) and a performance (speed) are considered. The problem is solved empirically by executing of experimental researches on the FSM benchmarks. Seven coding styles in Verilog are offered for coding of combinational circuits for FSMs from those two best styles are selected. On the basis of these two coding styles of combinational circuits six coding styles of FSMs are offered. The efficiency of the coding styles was researched for the synthesis of FSM benchmarks in two classes of programmable devices: CPLD (Complex programmable Logic Device) and FPGA. The experimental results showed that the choice of coding styles allows to reduce the implementation cost of FSMs by a factor of 3.06 and to increase the speed of FSMs by a factor of 1.6. In conclusion, the prospective directions for coding styles of FSMs are specified.

关键词： Finite state machine field programmable gate array Coding styles Verilog CPLD FPGA Implementation cost Speed CAD

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The Implementation of AES-CMAC Authenticated Encryption Algorithm on FPGA 2

The Implementation of AES-CMAC Authenticated Encryption Algo...

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2nd IEEE International Conference on Computer and Communication Engineering Technology (CCET)

作者： Pirzada, Syed Jahanzeb Hussain Murtaza, Abid Hasan, Muhammad Noman Xu, Tongge Liu Jianwei Beihang Univ Sch Cyber Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781728128719

The advancements in communication technology have evolved the algorithms used for communication security. Recently, the Authenticated Encryption (AE) algorithms are employed for providing security services for data communication. The Advanced Encryption Standard in Counter mode (AES-CTR) with Cipher-block Chaining Message authentication code (AES-CCM) algorithm is used for providing the data security for various applications. But the AES-CCM algorithm provides limited throughput for data communication. Therefore, in this work, new architecture is proposed for increase in throughput for provision of data security for communication application. The proposed algorithm uses the AES-CTR algorithm with the Cipher-based Message Authentication Code (CMAC) algorithm for providing AE. The proposed AE algorithm is implemented on FPGA and it's compared with the FPGA implementation of AES-CCM algorithm. The comparison results of the proposed algorithm and the AES-CCM algorithm shows that the proposed algorithm provides improvement in the consumption of the area, processing time, and throughput. The implementation of proposed AES-CMAC AE algorithm on FPGA provides a throughput of 4.30 Gbps.

关键词： advanced encryption standard authenticated encryption cipher-based message authentication code field programmable gate array

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Real-Time Experimental Demonstration of Multi-band CAP Modulation in a VLC System with Off-the-Shelf LEDs

Real-Time Experimental Demonstration of Multi-band CAP Modul...

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IEEE Conference on Computer Communications (IEEE INFOCOM)

作者： Haigh, Paul Anthony Darwazeh, Izzat UCL Commun & Informat Syst Grp Gower St London WC1E 6BT England

ISBN: (纸本)9781728118789

We demonstrate, for the first time, m-CAP modulation using off-the-shelf LEDs in a VLC in real time experimental setup using field programmable gate arrays based in universal software radio peripherals (USRPs). We demonstrate transmission speeds up to similar to 30 Mb/s can be achieved, which supports high definition television streaming.

关键词： Digital signal processing field programmable gate array modulation real time visible light communications

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Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array

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IET COMPUTERS AND DIGITAL TECHNIQUES 2011年第4期5卷 271-286页

作者： Angelopoulou, M. E. Bouganis, C-S. Cheung, P. Y. K. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2BT England

Restoration methods, such as super-resolution (SR), largely depend on the accuracy of the point spread function (PSF). PSF estimation is an ill-posed problem, and a linear and uniform motion is often assumed. In real-life systems, this may deviate significantly from the actual motion, impairing subsequent restoration. To address the above, this work proposes a dynamically configurable imaging system that combines algorithmic video enhancement, field programmable gate array (FPGA)-based video processing and adaptive image sensor technology. Specifically, a joint blur identification and validation (BIV) scheme is proposed, which validates the initial linear and uniform motion assumption. For the cases that significantly deviate from that assumption, the real-time reconfiguration property of an adaptive image sensor is utilised, and the sensor is locally reconfigured to larger pixels that produce higher frame-rate samples with reduced blur. Results demonstrate that once the sensor reconfiguration gives rise to a valid motion assumption, highly accurate PSFs are estimated, resulting in improved SR reconstruction quality. To enable real-time reconstruction, an FPGA-based BIV architecture is proposed. The system's throughput is significantly higher than 25 fps, for frame sizes up to 1024 x 1024, and its performance is robust to noise for signal-to-noise ratio (SNR) as low as 20 dB.

关键词： adaptive image sensor technology algorithmic video enhancement Video signal processing Logic and switching circuits point spread function imaging techniques autocorrelation-based blur identification framework Logic circuits image reconstruction sensor-based video reconstruction method field programmable gate arrays passive cameras Optical, image and video signal processing high-throughput hardware architecture Computer vision and image processing techniques image enhancement field programmable gate array image motion analysis joint blur identification and validation scheme Image sensors improved SR reconstruction quality image sensors system throughput signal-to-noise ratio

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Enhancing Trust In Autonomous Systems Without Verifying Software

Enhancing Trust In Autonomous Systems Without Verifying Soft...

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作者： Joseph Allan Stamenkovich Virginia Polytechnic Institute and State University

学位级别：硕士

The complexity of the software behind autonomous systems is rapidly growing, as are the applications of what they can do. It is not unusual for the lines of code to reach the millions, which adds to the verification challenge. The machine learning algorithms involved are often "black boxes" where the precise workings are not known by the developer applying them, and their behavior is undefined when encountering an untrained scenario. With so much code, the possibility of bugs or malicious code is considerable. An approach is developed to monitor and possibly override the behavior of autonomous systems independent of the software controlling them. Application-isolated safety monitors are implemented in configurable hardware to ensure that the behavior of an autonomous system is limited to what is intended. The sensor inputs may be shared with the software, but the output from the monitors is only engaged when the system violates its prescribed behavior. For each specific rule the system is expected to follow, a monitor is present processing the relevant sensor information. The behavior is defined in linear temporal logic (LTL) and the associated monitors are implemented in a field programmable gate array (FPGA). An off-the-shelf drone is used to demonstrate the effectiveness of the monitors without any physical modifications to the drone. Upon detection of a violation, appropriate corrective actions are persistently enforced on the autonomous system.

关键词： Autonomy Runtime Verification FPGA field programmable gate array Monitor Formal Methods UAS UAV Security Linear Temporal Logic LTL High-Level Synthesis HLS monitor model checking drone malware assurance robotics firmware hardware

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