检索结果-内蒙古大学图书馆

Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s

IET CIRCUITS DEVICES & SYSTEMS 2011年第4期5卷 321-328页

作者： Desmouliers, C. Oruklu, E. Saniie, J. IIT Dept Elect & Comp Engn Chicago IL 60616 USA

Designing a universal embedded hardware architecture for discrete wavelet transform is a challenging problem because of the diversity among wavelet kernel filters. In this work, the authors present three different hardware architectures for implementing multiple wavelet kernels. The first scheme utilises fixed, parallel hardware for all the required wavelet kernels, whereas the second scheme employs a processing element (PE)-based datapath that can be configured for multiple wavelet filters during run-time. The third scheme makes use of partial run-time configuration of FPGA units for dynamically programming any desired wavelet filter. As a case study, the authors present FPGA synthesis results for simultaneous implementation of six different wavelets for the proposed methods. Performance analysis and comparison of area, timing and power results are presented for the Virtex-II Pro FPGA implementations.

关键词： partial run-time configuration filters universal embedded hardware architecture discrete wavelet transform wavelet kernel filter processing element-based datapath run-time reconfiguration discrete wavelet transforms field programmable gate array Virtex-II Pro FPGA field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in field programmable gate arrays: An Experimental Case Study

引用

ENERGIES 2018年第4期11卷 739页

作者： Conti, Vincenzo Rundo, Leonardo Billeci, Giuseppe Dario Militello, Carmelo Vitabile, Salvatore Univ Enna KORE Fac Engn & Architecture I-94100 Enna Italy Univ Milano Bicocca Dept Informat Syst & Commun DISCo I-20126 Milan Italy CNR Italian Natl Res Council Inst Mol Bioimaging & Physiol IBFM I-90015 Cefalu Italy Univ Palermo Dept Biopathol & Med Biotechnol DIBIMED I-90133 Palermo Italy

Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration technique can be used to enable energy efficiency in a generic IoT node that exploits a field programmable gate array (FPGA) device. Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices. Exploiting the ability of reconfiguring circuit portions at runtime, the latest generation of FPGAs can be used to foster a better balance between energy consumption and performance. More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard. To this aim, a case study of a video filtering system is proposed and analyzed by dynamically loading three different hardware filters from the management software running on a Linux-based device. With more details, the presented analytical framework allows for a direct comparison between the energy efficiency of a dynamic partially reconfigurable device and a static non-reconfigurable one. The estimated timing conditions that allow the dynamic partially reconfigurable process to achieve relevant energy efficiency with respect to the corresponding static architecture are also outlined.

关键词： energy efficiency dynamic partial reconfiguration field programmable gate array digital signal processing video filtering

来源：评论

学校读者我要写书评

暂无评论

Compact Low-Cost Ultra-Wideband Pulsed-Radar System

Compact Low-Cost Ultra-Wideband Pulsed-Radar System

引用

作者： Aaron D. Pitcher McMaster University

学位级别：硕士

Recently, the advent of the integrated circuits (ICs), the monolithic microwave integrated circuits (MMICs) and the multiprocessing computer technology have provided numerous opportunities to make the radar technology compact and affordable. The ultra-wideband (UWB) technology gives many advantages over the traditional narrowband radar systems due to its high spatial resolution, low susceptibility to interference, superior penetration depths, and increased peak power. However, the ability to digitize and reconstruct the full UWB signal spectrum comes at a considerable cost and size. Ultimately, high-speed sampling rates above 10 giga-samples per second (GSPS) are beyond the abilities of conventional analog-to-digital converters (ADCs). The UWB technology is inaccessible to the end-user for various advanced applications in microwave imaging and detection. The purpose of this work is to provide a low-cost, dual-channel UWB pulsed-radar system that is readily available with a 1:10 system bandwidth. The advancements in low-cost alternatives for compact and portable designs empower many promising UWB applications. Here, the desired bandwidth is from 500 MHz to 5 GHz, which utilizes a fast pulse repetition frequency (PRF) in short-range applications. The preliminary results from the novel Equivalent-Time Sampling Receiver are promising with an equivalent-time sampling rate up to 20 GSPS. Nevertheless, the system design is versatile for bandwidth tuning in order to meet the needs of different applications. This versatility is enabled by: i) selection of the effective sampling rate through the field-programmable gate array (FPGA) programming environment, ii) choice of the receivers' front-end track and hold (T & H) amplifier bandwidth, iii) a collection of different PRFs from the low kilohertz up to 20 MHz, iv) tuning of the pulse generator bandwidth, and v) simultaneous multi-channel capabilities enabling antenna beam-forming, polarization diversity and spatial diversity.

关键词： Radar Ultra Wideband Radar field programmable gate array Microwave Circuits Microwave Sensors Sampling Methods

来源：评论

学校读者我要写书评

暂无评论

Methodologies for FPGA Implementation of Finite Control Set Model Predictive Control for Electric Motor Drives

Methodologies for FPGA Implementation of Finite Control Set ...

引用

作者： Lao, Alex McMaster University

学位级别：硕士

Model predictive control is a popular research focus in electric motor control as it allows designers to specify optimization goals and exhibits fast transient response. Availability of faster and more affordable computers makes it possible to implement these algorithms in real-time. Real-time implementation is not without challenges however as these algorithms exhibit high computational complexity. field-programmable gate arrays are a potential solution to the high computational requirements. However, they can be time-consuming to develop for. In this thesis, we present a methodology that reduces the size and development time of field-programmable gate array based fixed-point model predictive motor controllers using automated numerical analysis, optimization and code generation. The methods can be applied to other domains where model predictive control is used. Here, we demonstrate the benefits of our methodology by using it to build a motor controller at various sampling rates for an interior permanent magnet synchronous motor, tested in simulation at up to 125 kHz. Performance is then evaluated on a physical test bench with sampling rates up to 35 kHz, limited by the inverter. Our results show that the low latency achievable in our design allows for the exclusion of delay compensation common in other implementations and that automated reduction of numerical precision can allow the controller design to be compacted.

关键词： fpga field programmable gate array fcs finite control set hdl hardware description language rtl register transfer level numerical precision satisfiability modulo theories mpc model predictive control word length optimization electric drive electric motor permanent magnet synchronous motor interval arithmetic control system digital control inverter fixed point real time

来源：评论

学校读者我要写书评

暂无评论

Electromagnetic emanation exploration in FPGA-based digital design

引用

Journal of Central South University 2019年第1期26卷 158-167页

作者： Van Toan NGUYEN Minh Tung DAM Jeong-Gun LEE E-SoC Laboratory/Smart Computing Laboratory Department of Computer Engineering Hallym University

As semiconductor technologies have been shrinking,the speed of circuits,integration density,and the number of I/O interfaces have been significantly *** a consequence,electromagnetic emanation(EME)becomes a critical issue in digital system *** devices must meet electromagnetic compatibility(EMC)requirements to ensure that they operate properly,and safely without interference.I/O buffers consume high currents when they *** bonding wires,and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference(EMI).Therefore,I/O switching activities significantly contribute to the *** this paper,we evaluate and analyze the impact of I/O switching activities on the *** will change the circuit configurations such as the supply voltage for I/O banks,their switching frequency,driving current,and slew ***,a trade-off between the switching frequencies and the number of simultaneous switching outputs(SSOs)is also considered in terms of ***,we evaluate the electromagnetic emissions that are associated with the different I/O switching *** results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and *** the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.

关键词： electromagnetic interference electromagnetic emanation near field emissions field programmable gate array slew rate

来源：评论

学校读者我要写书评

暂无评论

FPGA IMPLEMENTATION SYSTEM FOR QRS COMPLEX DETECTION

引用

BIOMEDICAL ENGINEERING-APPLICATIONS BASIS COMMUNICATIONS 2020年第1期32卷

作者： Meddah, Karim Talha, Malika Kedir Hadjer, Zairi Nouah, Mohammed Hadji, Said Ait, Mohammed A. Bessekri, Besma Hachemi, Cherrih Houari Boumediene Univ Sci & Technol USTHB Dept Elect & Comp Sci BP32 El Alia Algiers 16111 Algeria

Due to the rising number of cardiovascular diseases death, the monitoring of cardiac patients has become a primary objective in the world. In this context, a fully FPGA-based system, for ECG signal monitoring and cardiac arrhythmia detection, has been proposed. The proposed QRS detection method is inspired by the Pan and Tompkins algorithm. It is optimized to be implemented in FPGA board Spartan 3 E (Nexys 2) using the VHDL language on the Xilinx ISE 14.2. In order to evaluate the effectiveness and reliability of our system, three comparative studies have been performed. The first comparison targeted the different results obtained with a floating-point representation under Matlab on one hand, and a fixed point representation under Xilinx ISE on the other hand, both using the MIT-BIH arrhythmia database records. The second comparison concerns the results obtained from the records of eight preselected subjects, with a commercialized electronic armband device ROMED BP-WR20 in a real-time test. The third is a comparison between the performance of our proposed method with the recent works in terms of reducing the FPGA resources list. The full embedded system has been realized completely from the signal acquisition to the display using the analog discovery device. The designed architecture has been validated using records obtained from the Massachusetts Institute of Technology - Beth Israel Hospital (MIT-BIH) arrhythmia database. It has also been validated in real-time via the analog discovery device. The overall accuracy and sensitivity are obtained as 97.6% and 97.3%, respectively.

关键词： field programmable gate array QRS detection Arrhythmia detection VHDL Electrocardiogram Heart rate MIT-BIH database

来源：评论

学校读者我要写书评

暂无评论

FPGA-based research of monitoring MPDCPD-CSMA protocol in cognitive wireless networks

引用

JOURNAL OF INTELLIGENT & FUZZY SYSTEMS 2018年第2期35卷 1353-1361页

作者： Xu, Zhi Ding, Hongwei Liu, Qianlin Yang, Zhijun Bao, Liyong Zhan, Gang Yunnan Univ Sch Informat Kunming 650504 Yunnan Peoples R China Yunnan Mil Command Reg Kunming Yunnan Peoples R China

In order to solve the contradiction between wireless network application requirements and increasingly scarce spectrum resources, cognitive wireless network technology emerged. Based on the characteristics of wireless network nodes and combining multiple hybrid control strategies, this paper proposes a multi-priority dual-clock probability detection CSMA(MPDCPD-CSMA) protocol with a monitoring mechanism. The field-programmable gate array (FPGA) hardware circuit is used as an experimental research platform for the first time. Cognitive wireless network MAC protocol design and implementation. The design took full advantage of the flexibility of the FPGA, using a hardware description language Verilog HDL and schematic input combined with the QuartusII9.0 circuit design. By comparing the statistical values of the circuit system with the theoretical values, it is verified that the design has the characteristics of good real-time performance, high reliability, and strong portability. It can effectively reduce system node energy consumption, improve system throughput, and can be applied to wireless networks.

关键词： cognitive wireless network hybrid control strategy field programmable gate array schematic input throughput

来源：评论

学校读者我要写书评

暂无评论

Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network

引用

IET CIRCUITS DEVICES & SYSTEMS 2018年第5期12卷 542-550页

作者： Murty, Mahesh S. Shrestha, Rahul Int Inst Informat Technol Hyderabad CVEST Hyderabad Telangana India Indian Inst Technol Mandi SCEE Suran Himachal Prades India

This paper presents reconfigurable and hardware-efficient VLSI architecture of time domain cyclostationary-feature detector (TCD) for spectrum sensing in the cognitive-radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE-Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware-efficient techniques have been introduced for the multiply-&-accumulate and accumulator architectures of suggested TCD design. Real-world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post-layout simulation of the proposed detector have been performed using 65 nm-CMOS technology and it occupies 0.32 mm(2) of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state-of-the-art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively.

关键词： spectrum sensor time-domain cyclostationary-feature detector spectrum sensing 4G LTE-Advanced rotation digital computer engine hardware-efficient techniques accumulator architectures performance analysis additive white Gaussian noise channel environment signal-to-noise ratios real-world signals universal software radio peripheral devices application specific integrated circuit synthesis post-layout simulation VLSI design orthogonal frequency division multiplexing OFDM signals multiply-&-accumulate architecture TCD design clock frequency overflow-underflow protection next-generation LTE-A cognitive-radio wireless network hardware-efficient very large-scale integration architecture autocorrelator OFDM-based communication system field programmable gate array FPGA united-microelectronics-corporation complementary metal–oxide–semiconductor technology frequency 1.0 MHz time 5.12 ms size 65.0 nm power 18.5 mW frequency 100.0 MHz Orthogonal frequency division multiplexing application specific integrated circuits field programmable gate arrays Very large scale integration Autocorrelators AWGN channels Wireless networks clock frequency

来源：评论

学校读者我要写书评

暂无评论

CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

引用

CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2018年第11期37卷 5101-5126页

作者： Kulshreshtha, Tanmai Dhar, Anindya Sundar Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

This paper presents a COordinate Rotation DIgital Computer (CORDIC)-based architecture of the sliding discrete Fourier transform (SDFT) for the real-time spectrum analysis with a refreshing mechanism through which the design can provide reduced and bounded error-accumulation due to the recursive nature of the existing SDFT algorithms. The proposed design is scalable with the transform length and the calculable number of the DFT bins, and can provide high throughput for a single bin evaluation. The paper also presents the comparison of the conventional and the modulated SDFT architectures based on CORDIC algorithm in terms of the angle-approximation and the truncation errors. The proposed design is synthesized on the Xilinx Virtex-6 FPGA platform and is implemented in ASIC using 90nm standard cell library.

关键词： COordinate Rotation DIgital Computer (CORDIC) Sliding discrete Fourier transform (SDFT) Real-time spectrum analysis field programmable gate array Application specific integrated circuit

来源：评论

学校读者我要写书评

暂无评论

Non-linear behavioural modelling of device-level transients for complex power electronic converter circuit hardware realisation on FPGA

引用

IET POWER ELECTRONICS 2018年第9期11卷 1566-1574页

作者： Lin, Ning Shi, Bo Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB Canada

Detailed device-level models of the insulated-gate-bipolar-transistor (IGBT) and diode are essential for power converter design evaluation for providing insight into circuit and device behaviours, as well as to shorten the design cycle and reduce costs. In this study, the non-linear behavioural models of IGBT and power diode are utilised for emulating the modular multilevel converter (MMC) on the field programmable gate array. For digital hardware-in-the-loop (HIL) emulation, these time-domain continuous models are discretised and linearised prior to being designed into the corresponding hardware modules using the hardware description language VHDL that features a fully paralleled and pipelined implementation. A circuit partitioning approach is adopted according to the MMC structure to enhance computation efficiency and then, detailed information from the system-level performance to the specific features of individual switches is available. HIL emulation and the subsequent comparison with results from the commercial off-line simulation tools prove that the complex IGBT and diode models can be involved in the efficient simulation of large-scale power converters.

关键词： field programmable gate arrays power convertors power semiconductor switches insulated gate bipolar transistors power semiconductor diodes time-domain analysis hardware description languages nonlinear behavioural modelling of device level transient model complex power electronic converter circuit hardware FPGA insulated-gate-bipolar-transistor IGBT power diode modular multilevel converter field programmable gate array digital hardware-in-the-loop emulation HIL emulation time domain continuous model hardware description language VHDL pipelined implementation circuit partitioning approach MMC structure switch

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：