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CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2018年第11期37卷 5101-5126页

作者： Kulshreshtha, Tanmai Dhar, Anindya Sundar Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

This paper presents a COordinate Rotation DIgital Computer (CORDIC)-based architecture of the sliding discrete Fourier transform (SDFT) for the real-time spectrum analysis with a refreshing mechanism through which the design can provide reduced and bounded error-accumulation due to the recursive nature of the existing SDFT algorithms. The proposed design is scalable with the transform length and the calculable number of the DFT bins, and can provide high throughput for a single bin evaluation. The paper also presents the comparison of the conventional and the modulated SDFT architectures based on CORDIC algorithm in terms of the angle-approximation and the truncation errors. The proposed design is synthesized on the Xilinx Virtex-6 FPGA platform and is implemented in ASIC using 90nm standard cell library.

关键词： COordinate Rotation DIgital Computer (CORDIC) Sliding discrete Fourier transform (SDFT) Real-time spectrum analysis field programmable gate array Application specific integrated circuit

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Non-linear behavioural modelling of device-level transients for complex power electronic converter circuit hardware realisation on FPGA

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IET POWER ELECTRONICS 2018年第9期11卷 1566-1574页

作者： Lin, Ning Shi, Bo Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB Canada

Detailed device-level models of the insulated-gate-bipolar-transistor (IGBT) and diode are essential for power converter design evaluation for providing insight into circuit and device behaviours, as well as to shorten the design cycle and reduce costs. In this study, the non-linear behavioural models of IGBT and power diode are utilised for emulating the modular multilevel converter (MMC) on the field programmable gate array. For digital hardware-in-the-loop (HIL) emulation, these time-domain continuous models are discretised and linearised prior to being designed into the corresponding hardware modules using the hardware description language VHDL that features a fully paralleled and pipelined implementation. A circuit partitioning approach is adopted according to the MMC structure to enhance computation efficiency and then, detailed information from the system-level performance to the specific features of individual switches is available. HIL emulation and the subsequent comparison with results from the commercial off-line simulation tools prove that the complex IGBT and diode models can be involved in the efficient simulation of large-scale power converters.

关键词： field programmable gate arrays power convertors power semiconductor switches insulated gate bipolar transistors power semiconductor diodes time-domain analysis hardware description languages nonlinear behavioural modelling of device level transient model complex power electronic converter circuit hardware FPGA insulated-gate-bipolar-transistor IGBT power diode modular multilevel converter field programmable gate array digital hardware-in-the-loop emulation HIL emulation time domain continuous model hardware description language VHDL pipelined implementation circuit partitioning approach MMC structure switch

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GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs

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IEEE TRANSACTIONS ON COMPUTERS 2018年第3期67卷 375-387页

作者： Wild, Alexander Moradi, Amir Gueneysu, Tim Ruhr Univ Bochum Horst Gortz Inst IT Secur D-44801 Bochum Germany Univ Bremen German Res Ctr Artificial Intelligence D-28359 Bremen Germany

Designers of secure hardware are required to harden their implementations against physical threats, such as power analysis attacks. In particular, cryptographic hardware circuits need to decorrelate their current consumption from the information inferred by processing (secret) data. A common technique to achieve this goal is the use of special logic styles that aim at equalizing the current consumption at each single processing step. However, since all hiding techniques like Dual-Rail Precharge (DRP) were originally developed for ASICs, the deployment of such countermeasures on FPGA devices with fixed and predefined logic structure poses a particular challenge. In this work, we propose and practically evaluate a new DRP scheme (GliFreD) that has been exclusively designed for FPGA platforms. GliFreD overcomes the well-known early propagation issue, prevents glitches, uses an isolated dual-rail concept, and mitigates imbalanced routings. With all these features, GliFreD significantly exceeds the level of physical security achieved by any previously reported, related countermeasures for FPGAs.

关键词： Dual-rail precharge logic field programmable gate array side-channel attack power analysis power-equalization hiding

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Dynamic Robust Single-Event Upset Simulator

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2018年第5期15卷 282-296页

作者： Carlisle, Edward George, Alan Univ Pittsburgh NSF Ctr Space High Performance & Resilient Comp Pittsburgh PA 15261 USA Univ Florida 560 Schenley Pl Pittsburgh PA 15213 USA Univ Pittsburgh NSF Ctr Space High Performance & Resilient Comp ECE 1238D Benedum Hall Pittsburgh PA 15261 USA

This paper presents the dynamic robust single-event upset simulator, which is a novel framework for fault injection on hardware (via onchip debugging) and simulation testbeds (via the Simics (R) full-system simulator from Wind River Systems). Typically, radiation-hardened processers are used for space computing;however, commercial off-the-shelf processors can provide higher performance and lower costs. Although commercial devices are susceptible to radiation-induced faults, fault-injection testing can be used to qualify these devices for use in space. The de facto standard for fault injection is radiation-beam testing, which is often prohibitively expensive and time consuming. The current methodology provides a means to iteratively decrease design vulnerabilities through rapid fault injection before beam testing. Additionally, the methodology can supplement beam-test results by targeting injections at individual components of interest that are difficult to isolate in beam tests. The current fault-injection mechanisms leverage on-chip debuggers and simulation checkpoints, allowing the framework to target a wide range of system components for injection. The injection capabilities and analysis features of the framework are demonstrated by presenting fault-injection results for an image-processing application on two different processor architectures (PowerPC and ARM (R)) in both hardware and simulation.

关键词： Fault Injection Image Processing Space Computing Commercial off the Shelf Debugger field programmable gate array Portable Operating System Feature Detection High Performance Reconfigurable Computing Random Access Memory

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Efficient FPGA-based VLSI architecture for detecting R-peaks in electrocardiogram signal by combining Shannon energy with Hilbert transform

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IET SIGNAL PROCESSING 2018年第6期12卷 748-755页

作者： Kumar, Madam Aravind Chari, Kamsali Manjunatha GVVIT Engn Coll Elect & Commun Engn Betapoodi Andhra Prades India GITAM Univ Elect & Commun Engn Visakhapatnam Andhra Prades India

Electrocardiogram (ECG) is a critical application in light of R-peak detection. The R-peaks are impacted by some QRS complex and noises in the current method. Basic testability, snappier execution, and confirmation choices are accomplished by the utilization of the field programmable gate array (FPGA). But, FPGA execution gives less accuracy. To battle execution trouble, another R-peak detector is proposed and relying upon the propelled peak finding logic, which incorporates a Bandpass filter and first-order differentiation process, which are done in the primary phase of the strategy. The noises in the input ECG signal are decreased in the first stage. In the subsequent stage, the smooth Shannon energy envelope (SEE) is acquired by utilizing SEE extraction and the zero phases filtering process. The false R peak is stifled by proposing a Hilbert transform (HT) in the third stage. The HT requires more hardware space and high-power utilization in the current technique. Due to this reason, Real valued Fast Fourier Transform (RFFT) and Inverse RFFT (IRFFT) techniques are proposed in the HT. In the fourth stage, R-peak acknowledgment is evaluated using Massachusetts Institute of Technology, Beth Israel Hospital (MIT-BIH) arrhythmia database and produced the average accuracy of 99.86%, sensitivity of 99.95% and the positive predictivity of 99.90%.

关键词： field programmable gate arrays biomedical electronics VLSI medical signal detection medical signal processing electrocardiography Hilbert transforms band-pass filters fast Fourier transforms feature extraction inverse transforms FPGA-based VLSI architecture R-peak detection electrocardiogram signal Shannon energy Hilbert transform snappier execution ECG QRS complex confirmation choices field programmable gate array R-peak pointer propelled peak finding logic bandpass filter first-order differentiation process smooth Shannon energy envelope SEE extraction zero phases filtering process high-power utilisation hardware space real valued fast Fourier transform strategy RFFT inverse RFFT techniques MIT-BIH arrhythmia database

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Timing error detection and correction for power efficiency: an aggressive scaling approach

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IET CIRCUITS DEVICES & SYSTEMS 2018年第6期12卷 707-712页

作者： Rathnala, Prasanthi Wilmshurst, Tim Kharaz, Ahmad Univ Derby Dept Elect Comp & Math Coll Engn & Technol Derby DE22 3AW England

Low-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low-power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time-borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip-flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two-stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.

关键词： error correction error detection power consumption flip-flops clocks field programmable gate arrays low-power electronics power efficiency aggressive scaling approach low-power consumption system level dynamic power supply voltage aggressive voltage scaling minimum power consumption aggressive frequency boosting time-borrowing feature system timing error tolerant error correction timing penalty power savings systems design processors error detection timing frequency varying hardware circuit flip-flop latch combination timing violation detection phase delaying field programmable gate array two-stage arithmetic pipeline

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Modeling, simulation, and implementation issues of CPGs for neuromorphic engineering applications

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COMPUTER APPLICATIONS IN ENGINEERING EDUCATION 2018年第4期26卷 782-803页

作者： Korkmaz, Nimet Ozturk, Ismail Kilic, Recai Erciyes Univ Dept Elect & Elect Engn TR-38039 Kayseri Turkey Amasya Univ Dept Elect & Elect Engn Amasya Turkey

Neuromorphic engineering is a discipline used to develop hardware, which can mimic the characteristics and abilities of biological systems by investigating their physiological structures and data transfer mechanisms. The recent studies about the neuromorphic systems mostly consist of robotic applications whose designs are inspired by Central Pattern Generators (CPGs). CPGs are special neural networks which can produce coordinated rhythmic activity patterns and these rhythmic movements are modeled mathematically, tested with simulation programs and verified by hardware implementations. A reconfigurable hardware platform (field programmable gate array FPGA) is compatible with numerical simulation tools, allows software control over hardware, has a user-friendly interface and allows real time modifications. Thus, recently, it is preferred in CPG based robotic applications. In this study, the details of the modeling, simulation and implementation stages of several CPG structures are introduced by using a digital reconfigurable hardware platform. In order to show the conceptual learning achievements of these stages and to assess the contribution to the modeling, simulation and implementation skills of the students, a training course has been planned for the undergraduate students at Erciyes University. This process has been held in an educative manner supported by a survey and an experimental examination, so that this training course has been evaluated by the trainees in terms of the advantage, practicality, and challenge.

关键词： Central Pattern Generators engineering education field programmable gate array neuromorphic engineering

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Improved Algorithms and Implementations for Integer to τNAF Conversion for Koblitz Curves

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第1期65卷 154-162页

作者： Li, Lijuan Li, Shuguo Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

The conversion from an integer scalar to a short and sparse tau-adic nonadjacent form (tau NAF) is crucial for efficient elliptic curve scalar multiplication over Koblitz curves. Currently the conversion is costly both in time and area, limiting the application of Koblitz curves. In this paper, we propose improved algorithms and implementations for both the single-digit and double-digit scalar conversions. Area reduction is achieved by removing the tau-and-add calculation of the remainder upon division by tau(m) for lazy reduction or the tau(2)-and-add one for the double lazy reduction. The tau NAF and the double tau NAF algorithms are modified accordingly to support a mixed-form-reduced scalar from the new reduction algorithms. Furthermore, fair pipelining is explored to speed up conversion with only a slight increase in area. Implementation results on Altera Stratix II FPGA show that the proposed single-digit converters are both smaller and faster than existing works, and the 4-stage pipelined one achieves at least 42.3% area reduction and 78.9% better area-time product (ATP) performance. On Xilinx Virtex IV, our non-pipelined double-digit converters are at least 44.5% smaller but slightly slower, while the 4-stage pipelined one can run faster with averagely 46.6% better ATP than previous equivalent works.

关键词： Elliptic curve cryptography Koblitz curves integer to tau NAF conversion lazy reduction field programmable gate array scalar multiplication

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A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第5期26卷 2194-2205页

作者： Alzaq, Husam Ustundag, Burak Berk Istanbul Tech Univ Fac Comp Engn Dept Comp Engn Istanbul Turkey

In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two key multiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS). Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection of the proper algorithm and implementation of multilevel DAA- and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs. The results reveal that the DAA-based approach is appropriate for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps, yet both DAA- and RNS-based approaches offer high signal quality with peak signal-to-noise ratio as 73.5 and 56.5 dB, respectively.

关键词： Discrete wavelet transform distributed arithmetic algorithm field programmable gate array residue number system

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Hardware variant NSP with security-aware automated preferential algorithm

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IET COMPUTERS AND DIGITAL TECHNIQUES 2018年第5期12卷 192-205页

作者： Paul, Rourab Sikder, Gitesh Chakrabarti, Amlan Ghosh, Ranjan Univ Calcutta Sch IT Kolkata India

Efficient and cost-effective hardware design of network security processor (NSP) is of vital importance in the present era due to the increasing need of security infrastructure in a wide range of computing applications. Here, the authors propose an NSP in field programmable gate array (FPGA) platform where according to a strict power, throughput, resource, and security priorities, a proposed preferential algorithm chooses a cipher suite to program the hardware. The choice is based on a rank list of available cipher suites depending on efficient system index evaluated in terms of power, throughput, resource, and security data and their given weights by the user. Encryption, hash, and key exchange algorithm along with their architectural variants serve excellent hardware flexibility whose bit files are stored in secure digital memory. The proposed design used an isolated key memory where secret keys are stored in encrypted form along with the hash value. The design is implemented using ISE14.4 suite with ZYNQ7z020-clg484 FPGA platform. The performances of the variants architecture of the crypto algorithms are considerably better in terms of power, throughput, and resource than the existing works reported in the literature.

关键词： field programmable gate arrays microprocessor chips cryptography logic design hardware variant NSP security-aware automated preferential algorithm cost-effective hardware design network security processor security infrastructure field programmable gate array preferential algorithm cipher suites system index security data key exchange algorithm architectural variants secure digital memory encryption secret keys hash value ZYNQ7z020-clg484 FPGA platform ISE14 4 suite crypto algorithms

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