Low-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the mo...
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Low-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low-power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time-borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip-flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two-stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.
Neuromorphic engineering is a discipline used to develop hardware, which can mimic the characteristics and abilities of biological systems by investigating their physiological structures and data transfer mechanisms. ...
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Neuromorphic engineering is a discipline used to develop hardware, which can mimic the characteristics and abilities of biological systems by investigating their physiological structures and data transfer mechanisms. The recent studies about the neuromorphic systems mostly consist of robotic applications whose designs are inspired by Central Pattern Generators (CPGs). CPGs are special neural networks which can produce coordinated rhythmic activity patterns and these rhythmic movements are modeled mathematically, tested with simulation programs and verified by hardware implementations. A reconfigurable hardware platform (field programmable gate array FPGA) is compatible with numerical simulation tools, allows software control over hardware, has a user-friendly interface and allows real time modifications. Thus, recently, it is preferred in CPG based robotic applications. In this study, the details of the modeling, simulation and implementation stages of several CPG structures are introduced by using a digital reconfigurable hardware platform. In order to show the conceptual learning achievements of these stages and to assess the contribution to the modeling, simulation and implementation skills of the students, a training course has been planned for the undergraduate students at Erciyes University. This process has been held in an educative manner supported by a survey and an experimental examination, so that this training course has been evaluated by the trainees in terms of the advantage, practicality, and challenge.
In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We present...
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In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two key multiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS). Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection of the proper algorithm and implementation of multilevel DAA- and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs. The results reveal that the DAA-based approach is appropriate for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps, yet both DAA- and RNS-based approaches offer high signal quality with peak signal-to-noise ratio as 73.5 and 56.5 dB, respectively.
Efficient and cost-effective hardware design of network security processor (NSP) is of vital importance in the present era due to the increasing need of security infrastructure in a wide range of computing application...
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Efficient and cost-effective hardware design of network security processor (NSP) is of vital importance in the present era due to the increasing need of security infrastructure in a wide range of computing applications. Here, the authors propose an NSP in field programmable gate array (FPGA) platform where according to a strict power, throughput, resource, and security priorities, a proposed preferential algorithm chooses a cipher suite to program the hardware. The choice is based on a rank list of available cipher suites depending on efficient system index evaluated in terms of power, throughput, resource, and security data and their given weights by the user. Encryption, hash, and key exchange algorithm along with their architectural variants serve excellent hardware flexibility whose bit files are stored in secure digital memory. The proposed design used an isolated key memory where secret keys are stored in encrypted form along with the hash value. The design is implemented using ISE14.4 suite with ZYNQ7z020-clg484 FPGA platform. The performances of the variants architecture of the crypto algorithms are considerably better in terms of power, throughput, and resource than the existing works reported in the literature.
In this paper, a novel design of Paillier encryption with a modified polar encoding is proposed and analyzed. A new cross-partitioned add shift processing element based on perfect reconstruction technique is designed ...
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In this paper, a novel design of Paillier encryption with a modified polar encoding is proposed and analyzed. A new cross-partitioned add shift processing element based on perfect reconstruction technique is designed for the realization of encryption with proper distribution of adders and shifters to minimize the logical component and register usage. In addition, a modified architecture for the polar encoder with optimal delay/minimized hardware resource is achieved by presenting a novel delay calculation methodology followed by register allocation grouped as the Reduced Register Delay Allocation (RRDA) algorithm. Resource utilization, including slice registers, lookuptables (LUTs) and DSP blocks are measured along with operating speed and throughput for the proposed paillier encryption and polar encoder. Finally, the performance is analyzed with the existing designs. The proposed sequential encoding-encryption can be deployed in imminent 5G systems. (C) 2017 Elsevier Ltd. All rights reserved.
Since the introduction of extreme ultraviolet (EUV) lithography (EUVL), the inevitable presence of EUV-induced plasmas inside the lithography tools impacts the operation of EUV optical components. EUV-induced plasmas ...
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Since the introduction of extreme ultraviolet (EUV) lithography (EUVL), the inevitable presence of EUV-induced plasmas inside the lithography tools impacts the operation of EUV optical components. EUV-induced plasmas are created everywhere in the optical path due to the ionizing interaction between the high energy (92 eV) EUV photons and the tools' background gas, which typically is hydrogen gas at a pressure of 1-10 Pa. From a physical point of view, the main impact of the plasma is due to the presence of ions that imping the plasma-facing surfaces. Experimental research into the fluence and energy distribution functions (IEDFs) of ions from EUV-induced plasmas has been limited to time-averaged measurements. In this Letter, we present time-resolved measurements of IEDFs for H+, H-2(+), and H-3(+) ions from an EUV-induced plasma in pure hydrogen gas. To this end, an electrostatic quadrupole plasma (EQP) analyzer has been used. The measurements pinpointed momentary fluxes up to three orders of magnitude higher than earlier reported average ion fluxes. In addition, the mean ion energy was unexpectedly found to remain elevated up to 50 mu s after the gas had been irradiated with EUV photons. Also, it was shown that the EQP detects H-2(+) ions on time scales much larger than expected. The presented results are valuable not only for the understanding of elementary processes regarding EUV-induced plasmas interacting with surfaces but also for simulating and predicting the impact of EUV-induced plasma on the lifetime and stability of optical components in EUVL.
This paper presents the description of a cyber-physical system embedded on an FPGA for 3D measurement in structural health monitoring tasks. The implementation technique and performance evaluation demonstrate the cont...
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This paper presents the description of a cyber-physical system embedded on an FPGA for 3D measurement in structural health monitoring tasks. The implementation technique and performance evaluation demonstrate the contribution of this paper to the mathematical fundamentals adaptation of an on-site rotatory scanning system to a cyber-physical system. In particular, it is described in detail the design of a virtual angle measurement soft sensing technique based on the information conversion of an optoelectronic signal provided by a rotatory scanning system through an FPGA. Behaving the FPGA as the sensor controller and the actuator in the scanning system. Using the measurement of angles through the proposed embedded system, it can be calculated the coordinates and displacement of specific indicators distributed over a structure under observation. Providing online data exchange from on-site measurement to a remote computational station for real-time or posteriorly data analysis.
This study proposes an efficient field programmable gate array (FPGA) implementation method of an enhanced space vector pulse width modulation (SVPWM) algorithm for a delta inverter. The overall hardware configuration...
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This study proposes an efficient field programmable gate array (FPGA) implementation method of an enhanced space vector pulse width modulation (SVPWM) algorithm for a delta inverter. The overall hardware configuration of the FPGA is made graphically using the high-level Xilinx system generator (XSG) programming tools. The proposed descriptive XSG model is first evaluated by running a hardware co-simulation test. The comparative study with computer simulations performed with Simulink shows a good agreement between the results of both methods, which approves the accuracy of the proposed descriptive XSG model. Moreover, an experimental test is carried out on a laboratory prototype of the delta inverter feeding an induction machine. The obtained high quality of the load currents confirms the feasibility of the proposed enhanced SVPWM algorithm and the effectiveness of its implementation method on FPGA.
The authors present initial results from the fourth-generation receiver for the Manastash Ridge radar, which is a distributed passive radar system used for ionospheric physics and engineering studies. This receiver pe...
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The authors present initial results from the fourth-generation receiver for the Manastash Ridge radar, which is a distributed passive radar system used for ionospheric physics and engineering studies. This receiver permits simultaneous access to the high-frequency (HF), very HF (VHF), and ultra HF (UHF) spectrum by sampling at speeds up to 5 billion samples/s on multiple antennas. This system has large aggregate bandwidth;it can simultaneously collect the entire VHF FM broadcast band as well as several UHF DTV broadcasts. The receiver adopts direct sampling architecture;therefore, high dynamic range is achieved with decimation for narrowband signals. Most of the analogue signal path is eliminated, yielding excellent linearity, and high-speed digital signal processing in the field programmable gate array (FPGA) yields low-latency real-time operation. The authors also discuss algorithms to make effective use of the FPGA. For example, the sampler runs 16 times faster than the FPGA, so initial FPGA processing requires parallel algorithms. In the authors design, the downconverter passband centre frequencies and spectral widths are selectable at run time, and can be changed in a few milliseconds. The authors FPGA computes in fixed point math, which presents both opportunities and challenges in managing precision during the signal processing for networking and for subsequent signal processing.
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