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Feedback compensated 10 kW solid-state pulsed power amplifier at 352 MHz for particle accelerators

REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第10期90卷 104707-104707页

作者： Duc, L. Hoang Jobs, M. Lofnes, T. Ruber, R. Olsson, J. Dancila, D. Angstrom Lab Div Solid State Elect S-75121 Uppsala Sweden Angstrom Lab Dept Phys & Astron S-75120 Uppsala Sweden

This paper presents the first results of an in-house developed low-level radio frequency (LLRF) system and a 10 kW solid state power amplifier (SSPA). The design approach for the SSPA is based on eight resonant single-ended kilowatt modules combined using a planar Gysel combiner. Each of the single-ended modules is based on a two-stepped impedance resonant matching, allowing for harmonic suppression, simple design for massive production, and high-performance design. A design methodology to tune SSPA modules for optimum combining efficiency is presented thoroughly in the time domain. We characterize the power droop due to capacitor banks in the time domain. In open loop of compensation, it is about 1 kW within the pulse of peak value 10 kW and a duration of 3.5 ms. This may lead to the beam instability of the accelerator as particles are not provided with the same energy during the pulse. By incorporating our LLRF system, it is demonstrated that the objective of amplitude and phase stability is satisfied, as required in the European Spallation Source proton accelerator. The presented design also offers the advantages of compact form factor, low complexity, and better performance. In closed loop compensation, the variation of amplitude (pulse droop) is measured on the order of 20 W, which is equivalent to 0.2% at 10 kW peak output power. (C) 2019 Author(s).

关键词： Particle accelerators Synchrotrons field programmable gate array Coaxial connectors Vacuum tubes Amplifiers Pulse generators Radiowave and microwave technology field effect transistors Transformer

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Prototyping and hardware-in-loop verification of OCR

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IET GENERATION TRANSMISSION & DISTRIBUTION 2018年第12期12卷 2837-2845页

作者： Kumar, Praveen Kumar, Vishal Pratap, Rajendra Indian Inst Technol Dept Elect Engn Roorkee Uttrakhand India

This study presents the design and development of a soft-core prototype of an overcurrent relay (OCR). The prototype is implemented on the field programmable gate array and its functionality has been verified using hardware-in-loop testing on the real-time digital simulator. Computational efficiency and memory requirement of the OCR is improved by using integer arithmetic Verilog design platform. Extreme inverse and very inverse characteristics of the OCR based on standard inverse-time characteristics as per IEEE standard C37.112-1996 is used and tested in the proposed design. Digital design of the proposed algorithm, emulation results, complete hardware setup and experimental test results are presented in this study. The performance of the OCR is evaluated for a large range of characteristic parameters (pick-up current and time-dial setting) and various operating conditions which validate the operation of the relay in real time with the power network. The designed relay has the ability to differentiate between fault and inrush current to avoid any mal-operation during energisation of transformers.

关键词： overcurrent protection relay protection field programmable gate arrays hardware description languages arithmetic inverse problems fault diagnosis power transformers hardware-in-loop verification OCR overcurrent relay field programmable gate array real-time digital simulator integer arithmetic Verilog design platform very inverse characteristics extreme inverse characteristics standard inverse-time characteristics IEEE C37 112-1996 standard power network transformer

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The Study on field programmable gate array based on PID Controllers in Real Time

The Study on Field Programmable Gate Array based on PID Cont...

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International Conference on Mechanical Materials and Manufacturing Engineering (ICMMME 2011)

作者： He Fang Xinyu University China

ISBN: (纸本)9783037851852

In the present work PID control and the fuzzy logic based intelligent control is used to control the rectilinear plant vibrations. PID controller in real time mode is implemented on FPGA. For implementation of fuzzy logic based intelligent controller the FPGA is used as real time data acquisition (DAQ) platform and the fuzzy controller is implemented on the host PC. The sole reason for using FPGA as data acquisition platform was that the LabVIEW FPGA software module is not supporting the complex mathematics required for the fuzzy logic control and also the rectilinear plant interface with the traditional DAQ was not available. The comparative study of performance of intelligent controllers like fuzzy PD and fuzzy PI+ fuzzy PD is done with the conventional controllers on the basis of above mentioned performance indices. The result of the fuzzy PI + fuzzy PD controller is found to be the best among all.

关键词： field programmable gate array Fuzzy Control Real Time

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Survey of deployment locations and underlying hardware architectures for contemporary deep neural networks

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INTERNATIONAL JOURNAL OF DISTRIBUTED SENSOR NETWORKS 2019年第8期15卷

作者： Kotlar, Milos Bojic, Dragan Punt, Marija Milutinovic, Veljko Univ Belgrade Sch Elect Engn Bulevar Kralja Aleksandra 73 Belgrade 11000 Serbia Indiana Univ Dept Comp Sci Bloomington IN 47405 USA

This article overviews the emerging use of deep neural networks in data analytics and explores which type of underlying hardware and architectural approach is best used in various deployment locations when implementing deep neural networks. The locations which are discussed are in the cloud, fog, and dew computing (dew computing is performed by end devices). Covered architectural approaches include multicore processors (central processing unit), manycore processors (graphics processing unit), field programmable gate arrays, and application-specific integrated circuits. The proposed classification in this article divides the existing solutions into 12 different categories, organized in two dimensions. The proposed classification allows a comparison of existing architectures, which are predominantly cloud-based, and anticipated future architectures, which are expected to be hybrid cloud-fog-dew architectures for applications in Internet of Things and Wireless Sensor Networks. Researchers interested in studying trade-offs among data processing bandwidth, data processing latency, and processing power consumption would benefit from the classification made in this article.

关键词： Application-specific integrated circuit big data cloud computing central processing unit deep neural networks dew computing edge computing fog computing field programmable gate array graphics processing unit

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A novel digital programmable multi-scroll chaotic system and its application in FPGA-based audio secure communication

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2018年 88卷 20-29页

作者： Chang, De Li, Zhijun Wang, Mengjiao Zeng, Yicheng Xiangtan Univ Coll Informat Engn Xiangtan 411105 Peoples R China Xiangtan Univ Sch Phys & Optoelect Xiangtan 411105 Peoples R China

In recent years, information security is an increasingly vital problem. In this paper, we introduce an audio encryption scheme based on the novel digital programmable multi-scroll chaotic system. The chaotic system is described by three differential equations with piecewise nonlinear functions. More interesting, the number of scrolls of the proposed chaotic system is programmable and can be changed real-time. The system is discretized by Euler method and the digital implementation is provided. Based on this, a chaos-based audio secure communication system is developed by using feedback drive-response synchronization. The number of scrolls changes randomly by extracting control signals from the encrypted data. A series of security analyses are applied, showing good performance of the method. The system is verified through experiment on an Altera Cyclone IV FPGA platform, which effectively confirms the theoretical analysis.

关键词： Chaos Secure communication Multi-scroll chaos field programmable gate array

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Bioelectronic organ-based sensor for microfluidic real-time analysis of the demand in insulin

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BIOSENSORS & BIOELECTRONICS 2018年 117卷 253-259页

作者： Perrier, R. Pirog, A. Jaffredo, M. Gaitan, J. Catargi, B. Renaud, S. Raoux, M. Lang, J. Univ Bordeaux CNRS Lab Chim & Biol Membranes & Nanoobjets CBMN UMR 5248 18 Av Geoffroy St Hilaire F-33600 Pessac France Univ Bordeaux CNRS Bordeaux INP Lab Integrat Mat Syst IMSUMR 5218 F-33400 Talence France Univ Bordeaux Bordeaux Univ Hosp Hop St Andre 1 Rue Jean Burguet F-33000 Bordeaux France Univ Paris Sud INSERM Signalisat Calc & Physiopathol Cardiovasc S1180 Paris France

On-line and real-time analysis of micro-organ activity permits to use the endogenous analytical power of cellular signal transduction algorithms as biosensors. We have developed here such a sensor using only a few pancreatic endocrine islets and the avoidance of transgenes or chemical probes reduces bias and procures general usage. Nutrient and hormone-induced changes in islet ion fluxes through channels provide the first integrative read-out of micro-organ activity. Using extracellular electrodes we captured this read-out non-invasively as slow potentials which reflect glucose concentration-dependent (3-15 mM) micro-organ activation and coupling. Custom-made PDMS-based microfluidics with platinum black micro-electrode arrays required only some tens of islets and functioned at flow rates of 1-10 mu l/min which are compatible with microdialysis. We developed hardware solutions for on-line real-time analysis on a reconfigurable field-programmable gate array (FPGA) that offered resource-efficient architecture and storage of intermediary processing stages. Moreover, real-time adaptive and reconfigurable algorithms accounted for signal disparities and noise distribution. Based on islet slow potentials, this integrated set-up allowed within less than 40 ps the discrimination and precise automatic ranking of small increases (2 mM steps) of glucose concentrations in real time and within the physiological glucose range. This approach shall permit further development in continuous monitoring of the demand for insulin in type 1 diabetes as well as monitoring of organs-on-chip or maturation of stem-cell derived islets.

关键词： Diabetes Islets Continuous glucose monitoring Micro-electrode arrays On-line real-time analysis field programmable gate array

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Reinforced Droop for Active Current Sharing in Parallel NPC Inverter for Islanded AC Microgrid Application

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ENERGIES 2019年第16期12卷 3090页

作者： Purushotham, Monica Muniswamy, Kowsalya Vellore Inst Technol Sch Elect Engn Vellore 632014 Tamilnadu India

The paper investigates the current sharing in parallel 3-level Neutral point clamped inverter for islanded AC microgrid application. In Distributed generation, parallel power electronic interface based microgrid suffers from power quality issues due to inaccurate output current sharing. To address the current sharing problem, the paper proposes an improved droop technique that reinforces the droop loop by infusing the incurred voltage drop accountable for inaccurate current sharing at the inverter output. The control based on droop reference is bounded with regard to output current since the output impedance influences the output current of the inverter largely. Besides that, the parallel NPC inverter also suffers from dc link voltage imbalance due to neutral currents. To address these issues a control strategy is proposed in the research work in which the processed DC offset is incorporated into the reinforced droop loop and the generated reference is utilized with feedback control to accurately share the currents under linear and nonlinear load conditions. The effectiveness of devised reinforced droop strategy is realized in MATLAB/Simulink environment and experimental validation is carried out with the field-programmable gate array as hardware interface to the hardware laboratory prototype of parallel NPC inverter.

关键词： distributed power generation 3-level Neutral point clamped inverter reinforced droop control field programmable gate array islanded microgrid circulating current

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A multifunction digital receiver suitable for real-time frequency detection and compensation in fast magnetic resonance imaging

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第5期90卷 053707-053707页

作者： Li, Limin Wyrwicz, Alice M. NorthShore Univ HealthSystem Ctr Basic MR Res Res Inst Evanston IL 60201 USA Northwestern Univ Dept Biomed Engn Evanston IL 60208 USA

We describe the development and implementation of a multifunction digital receiver suitable for magnetic resonance imaging with capability of real-time frequency detection and compensation. The digital receiver consists primarily of firmware modules that combine the functionalities of signal acquisition, frequency detection and compensation, and data correction and image reconstruction. The receiver was developed based on a single multiple-input multiple-output radio-frequency electronic board equipped with a reconfigurable field programmable gate array (FPGA) device. A simple and practical algorithm was developed and implemented on the FPGA to accelerate the data processing for frequency determination. The simplified frequency detection and the higher system integration enable the receiver to reduce dramatically the time for frequency detection and compensation. With this receiver, we are able to detect the frequency of short-duration signals in the bandwidth of 10 MHz centered at 400 MHz within 75 ns after the signal acquisition. We describe the designs of the key FPGA modules and how these modules integrate into a multifunction receiver. We also present testing data that validate the simplified algorithm for frequency determination, demonstrate frequency detection and compensation, and demonstrate how real-time data correction is performed during image acquisition and reconstruction. Published under license by AIP Publishing.

关键词： Digital signal processing Magnetic resonance imaging field programmable gate array Magnetic fields Frequency measurement

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Calibration of DC offsets in quadrature mixing structure based on Hilbert transform

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第5期90卷 054701-054701页

作者： Guo, Lianping Ye, Peng Tian, Yu Zeng, Hao Meng, Jie Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Sichuan Peoples R China

DC offsets in a quadrature mixing structure will affect the system performance. This paper proposes a Hilbert transform-based algorithm to blindly calibrate the DC offsets by filtering the inphase and quadrature signals with the same Hilbert filters. Compared with the traditional averaging-based method, this method consumes less time and resources. Moreover, the proposed method need not interrupt analog-to-digital converter's conversion, featuring the characteristics of high efficiency and good real-time performance. The Matlab simulation results verify the correctness of the proposed algorithm, and finally, an experimental platform is designed in detail to verify the practicability of this blind calibration algorithm. Published under license by AIP Publishing.

关键词： Signal processing Demodulators Linear filters Fourier analysis Analog-to-digital converter Frequency spectrum field programmable gate array

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Heterogeneous Sensor Data Analysis Using Efficient Adaptive Artificial Neural Network on FPGA Based Edge gateway

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KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS 2019年第10期13卷 4865-4885页

作者： Gaikwad, Nikhil B. Tiwari, Varun Keskar, Avinash Shivaprakash, N. C. Indian Inst Sci IISc Dept Instrumentat & Appl Phys CV Raman Ave Bengaluru 560012 India

We propose a FPGA based design that performs real-time power-efficient analysis of heterogeneous sensor data using adaptive ANN on edge gateway of smart military wearables. In this work, four independent ANN classifiers are developed with optimum topologies. Out of which human activity, BP and toxic gas classifier are multiclass and ECG classifier is binary. These classifiers are later integrated into a single adaptive ANN hardware with a select line( s) that switches the hardware architecture as per the sensor type. Five versions of adaptive ANN with different precisions have been synthesized into IP cores. These IP cores are implemented and tested on Xilinx Artix-7 FPGA using Microblaze test system and LabVIEW based sensor simulators. The hardware analysis shows that the adaptive ANN even with 8-bit precision is the most efficient IP core in terms of hardware resource utilization and power consumption without compromising much on classification accuracy. This IP core requires only 31 microseconds for classification by consuming only 12 milliwatts of power. The proposed adaptive ANN design saves 61% to 97% of different FPGA resources and 44% of power as compared with the independent implementations. In addition, 96.87% to 98.75% of data throughput reduction is achieved by this edge gateway.

关键词： Real-time data analysis field programmable gate array adaptive artificial neural network edge gateway fog computing smart wearables

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