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Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2018年 891卷 37-41页

作者： Kuang, Jie Wang, Yonggang Cao, Qiang Liu, Chong Univ Sci & Technol China Dept Modern Phys Hefei 230026 Anhui Peoples R China

Time-to-digital convertors (TDCs) based on field programmable gate array (FPGA) are becoming more and more popular. Multi-measurement is an effective method to improve TDC precision beyond the cell delay limitation. However, the implementation of TDC with multi-measurement on FPGAs manufactured with 28 nm and more advanced process is facing new challenges. Benefiting from the ones-counter encoding scheme, which was developed in our previous work, we implement a ring oscillator multi-measurement TDC on a Xilinx Kintex-7 FPGA. Using the two TDC channels to measure time-intervals in the range (0 ns-30 ns), the average RMS precision can be improved to 5.76 ps, meanwhile the logic resource usage remains the same with the one-measurement TDC, and the TDC dead time is only 22 ns. The investigation demonstrates that the multi-measurement methods are still available for current main-stream FPGAs. Furthermore, the new implementation in this paper could make the trade-off among the time precision, resource usage and TDC dead time better than ever before.

关键词： Time-to-digital converter Multi-measurement Time precision Measurement dead time field programmable gate array

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A family of conservative chaotic systems with cyclic symmetry

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PRAMANA-JOURNAL OF PHYSICS 2019年第4期92卷 48-48页

作者： Gugapriya, G. Rajagopal, Karthikeyan Karthikeyan, Anitha Lakshmi, B. Vellore Inst Technol Sch Elect Engn Chennai 600127 Tamil Nadu India Ctr Nonlinear Dynam Def Univ Bishoftu Ethiopia

In this paper, we propose a family of circulant systems with conservative property. Various dynamical properties of the circulant systems are derived and investigated. Bifurcation plots are derived and presented for a system and the Lyapunov exponents are derived to show the existence of chaotic oscillations, and their sum being zero confirms the conservativeness for certain values of parameters. One of the proposed systems is then implemented in field programmable gate array (FPGA) to show the hardware reliability. We used the hardware-software co-simulation to see the phase portraits of the FPGA implemented system. The discrete integrators required for solving the initial value problem are implemented using the Euler's method. The register transfer level schematics of the FPGA implemented system and the resources used for the implementations are presented.

关键词： Cyclic symmetry system Lyapunov exponents bifurcation plots field programmable gate array

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An open-source high-frequency lock-in amplifier

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第9期90卷 094701-094701页

作者： Stimpson, G. A. Skilbeck, M. S. Patel, R. L. Green, B. L. Morley, G. W. Univ Warwick Dept Phys Coventry CV4 7AL W Midlands England Univ Warwick Diamond Sci & Technol Ctr Doctoral Training Gibbet Hill Rd Coventry CV4 7AL W Midlands England

We present characterization of a lock-in amplifier based on a field programmable gate array capable of demodulation at up to 50 MHz. The system exhibits 90 nV/root Hz of input noise at an optimum demodulation frequency of 500 kHz. The passband has a full-width half-maximum of 2.6 kHz for modulation frequencies above 100 kHz. Our code is open source and operates on a commercially available platform.

关键词： Infinite impulse response Signal processing Demodulators Direct digital synthesis Digital-to-analog converter Software engineering Fourier analysis Amplifiers Telecommunications engineering field programmable gate array

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Accelerated Architectures Create Programming Opportunities

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COMPUTER 2018年第6期51卷 82-85页

作者： DeBenedictis, Erik P. Sandia Natl Labs Ctr Comp Res Livermore CA 94550 USA

In the early 2000s, industry switched to multicore microprocessors to address semiconductors' speed and power limits. However, the change was unsuccessful, leading to dire claims that "Moore's law is ending." This column suggests that while the approach was sound, it needed a deeper architectural transformation. Industry has since discovered a suitable architecture, but work remains on software to support it.

关键词： Microprocessor Chips Multiprocessing Systems Software Architecture Accelerated Architectures Programming Opportunities Microprocessors Semiconductors Moores Law Deeper Architectural Transformation Computer Architecture Hardware Microprocessors field programmable gate arrays Micromechanical Devices Programming Rebooting Computing field programmable gate array FPGA Custom Chip ASIC Application Specific Integrated Circuit Moore X 2019 S Law Von Neumann Architecture Multicore Logic Synthesis Accelerator Hardware High Performance Computing

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Digital instrument with configurable hardware and firmware for multi-channel time measures

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第5期90卷 055113-055113页

作者： Lusardi, Nicola Garzetti, Fabio Geraci, Angelo Politecn Milan DEIB Via Camillo Golgi 40 I-20133 Milan MI Italy

A new digital instrument for timing of events is presented. It is based on a reconfigurable, high-performance, 16-channel time-to-digital converter implemented in a Xilinx 7 Series 28-nm field programmable gate array device. Each channel provides timestamps with a least significant bit of 2 ps that states the resolution, whereas instead the single-shot precision is below 12.5 ps rms with the possibility of multihit measures at the maximum rate of 20 MHz. The default width of the full-scale range is 157 mu s that can be extended at users choosing up to 15 days by means of proper time tagging procedures made available. The instrument achieves performance in terms of precision, resolution, and full-scale range of measurement at the state-of-art of existing solutions. The novelty is that besides performance, the presented instrument is totally reconfigurable by the user both in the hardware and in the firmware parts. Moreover, novel techniques of event acquisition (e.g., level-zero trigger) are introduced. These further features are not present in any other instrument available nor in the literature or in commerce and constitute a difference with respect to all referenced instruments. Published under license by AIP Publishing.

关键词： Logic gates Analog circuits field programmable gate array Delay lines Nanowires Chemical elements Comparators Real-time process Time-to-digital converter Energy use and applications

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Bandwidth Efficient Frame Structure Algorithm and Analysis: An Extension to Telemetry Standard

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2019年第12期16卷 534-545页

作者： Rafique, Muhammad Abdullah Adeel, Muhammad Ctr Excellence Sci & Appl Technol Elect Engn Dept Islamabad 44000 Pakistan Hong Kong Polytech Univ EIE Dept Kowloon Hong Kong Peoples R China

An onboard telemetry system has access to a limited wireless bandwidth due to a high-speed airborne vehicle and large channel changing characteristics. The inefficiency of data placement happens at the transmission end if there is a large deviation between the packet rate and the frame rate for serial channels. For one of the current examples, the data rate of the transmitted signal can be decreased from 22 Mbps by straightforward placement in the major frame and to 3 Mbps using the novel algorithm introduced in this paper. The mathematical model in the subject is termed the bandwidth-efficient frame structure algorithm. A Xilinx Spartan 3E series has been used to frame the acquired data at the transmitting end and to deframe at the receiving end. The Inter-Range Instrumentation Group 106 standard has been used for the frame structure.

关键词： Telemetry System Mathematical Models Data Acquisition System field programmable gate array Universal Asynchronous Receiver Transmitter Optimization Algorithm Data Transmission Global Positioning System Seismology Computing

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Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2019年 944卷 162584-162584页

作者： Song, Zhengqi Wang, Yonggang Kuang, Jie Univ Sci & Technol China Dept Modern Phys Hefei 230026 Anhui Peoples R China

Unlike the conventional field programmable gate array (FPGA) based time-to-digital converter (TDC) with clock sampling architecture, the TDC with event sampling architecture implemented in this paper propagates the system clock signal along the tapped-delay line (TDL) and the TDL status is sampled by a hit signal for time interpolation. Since there are several "1-0" and "0-1" transitions in the sampled TDL status, the TDC naturally realizes multiple measurements in parallel without increasing the resource consumption and the measurement dead time. Using a Xilinx Kintex-7 FPGA, we increase the number of equivalent TDC bins approximately to twice the number of physical delay cells in the TDL, which means the TDC resolution is about twice as good as the original. The average RMS precision is measured as 5.3 ps with two identical TDC channels measuring the time intervals in the range 0 to 20 ns. The proposed encoding scheme is so efficient that the TDC measurement throughput can reach 350 M samples per second. The test results show that the event sampling architecture is effective in FPGA as well. The performance that can be achieved is comparable with the performance of their counterparts that use the clock sampling architecture.

关键词： Time-to-digital converter field programmable gate array Multi-measurement Encoder Measurement throughput

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Simulation and modelling of long term reliability of digital circuits implemented in FPGA

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MICROELECTRONICS RELIABILITY 2018年第Sep.期88-90卷 1130-1134页

作者： Morales, J. D. Aguirre Marc, F. Bensoussan, A. Durier, A. Univ Bordeaux Lab IMS Talence France IRT St Exupery Toulouse France

In this work, we report on the development of a methodology for long term reliability analysis of digital circuits implemented in FPGA. For this, a simulation environment for FPGA has been extended using Python to introduce aging. The aging laws for Look-Up Tables have been integrated by introducing additional variables and equations. They accurately describe the drifts in the propagation time caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms. An analytical model of the failure time of the digital circuit as a function of the clock frequency has been proposed based on the aging law parameters. Finally, the developed methodology has been applied to a CORDIC circuit implemented in FPGA.

关键词： Reliability Modelling Simulation Digital circuits field programmable gate array Negative bias thermal instability Hot Carrier Injection

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Undeviating Adaptive Sheltered Cryptography (UASC) method based low power and high secure cache memory design

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MICROPROCESSORS AND MICROSYSTEMS 2019年 71卷 102876-000页

作者： Sai, R. Vijay Upadhyay, Har Narayan Prabhu, M. Saravanan, S. SASTRA Deemed Univ Sch Comp Thanjavur Tamil Nadu India SASTRA Deemed Univ Sch Elect & Elect Engn Thanjavur Tamil Nadu India

The prerequisite of data security on network has turned out to be more important. Cryptography is a technique to give data privacy, acceptability and integrity. There are such significant number of difficulties to realize cryptography algorithm, for example, execution time, memory requirement, and intention control. In this work, a high secure and low power use of cache memory is implemented for utilizing a new cryptography method specifically named as Undeviating Adaptive Sheltered Cryptography (UASC) algorithm. The outline of the proposed memory has been altered by the expansion of all validation supervisors required by the equipment usage of Advanced Encryption Standard (AES). In addition, UASC has been incorporated into real time application to permit a self-encryption based on full self-rule. Therefore, compared with the conventional design comprising of a crypto-block and an isolated memory, this new method will prompt an imperative decrease of data interactions among the encryption procedure. The proposed work is depicted utilizing Verilog language, synthesized and actualized utilizing Xilinx ISE suite based field programmable gate array (FPGA) devices. Synthesis results demonstrate that the proposed configuration accomplishes higher efficiency than the previous executions by decreasing area while keeping up a moderate throughput/Look UpTable (LUT) ratio. The proposed configuration is additionally more productive as far as power utilization is concerned. As compared with conventional method, the proposed Undeviating Adaptive Sheltered Cryptography achieves low power consumption for 23.02 mu w and execution time is 9.5 s. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Cache memory Encryption Decryption Undeviating Adaptive Sheltered Cryptography field programmable gate array

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A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第4期90卷 044706-044706页

作者： Xia, Haojie Cao, Guiping Dong, Ning Hefei Univ Technol Sch Instrument Sci & Optoelect Engn Hefei 230009 Anhui Peoples R China Hefei I Tek OptoElect Co Ltd China Res Ctr High Speed Machine Vis Hefei 230088 Anhui Peoples R China

Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit. Published under license by AIP Publishing.

关键词： Digital circuits Interpolation Time-to-digital converter field programmable gate array Delay lines Electronic circuits

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