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Bandwidth Efficient Frame Structure Algorithm and Analysis: An Extension to Telemetry Standard

JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2019年第12期16卷 534-545页

作者： Rafique, Muhammad Abdullah Adeel, Muhammad Ctr Excellence Sci & Appl Technol Elect Engn Dept Islamabad 44000 Pakistan Hong Kong Polytech Univ EIE Dept Kowloon Hong Kong Peoples R China

An onboard telemetry system has access to a limited wireless bandwidth due to a high-speed airborne vehicle and large channel changing characteristics. The inefficiency of data placement happens at the transmission end if there is a large deviation between the packet rate and the frame rate for serial channels. For one of the current examples, the data rate of the transmitted signal can be decreased from 22 Mbps by straightforward placement in the major frame and to 3 Mbps using the novel algorithm introduced in this paper. The mathematical model in the subject is termed the bandwidth-efficient frame structure algorithm. A Xilinx Spartan 3E series has been used to frame the acquired data at the transmitting end and to deframe at the receiving end. The Inter-Range Instrumentation Group 106 standard has been used for the frame structure.

关键词： Telemetry System Mathematical Models Data Acquisition System field programmable gate array Universal Asynchronous Receiver Transmitter Optimization Algorithm Data Transmission Global Positioning System Seismology Computing

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Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2019年 944卷 162584-162584页

作者： Song, Zhengqi Wang, Yonggang Kuang, Jie Univ Sci & Technol China Dept Modern Phys Hefei 230026 Anhui Peoples R China

Unlike the conventional field programmable gate array (FPGA) based time-to-digital converter (TDC) with clock sampling architecture, the TDC with event sampling architecture implemented in this paper propagates the system clock signal along the tapped-delay line (TDL) and the TDL status is sampled by a hit signal for time interpolation. Since there are several "1-0" and "0-1" transitions in the sampled TDL status, the TDC naturally realizes multiple measurements in parallel without increasing the resource consumption and the measurement dead time. Using a Xilinx Kintex-7 FPGA, we increase the number of equivalent TDC bins approximately to twice the number of physical delay cells in the TDL, which means the TDC resolution is about twice as good as the original. The average RMS precision is measured as 5.3 ps with two identical TDC channels measuring the time intervals in the range 0 to 20 ns. The proposed encoding scheme is so efficient that the TDC measurement throughput can reach 350 M samples per second. The test results show that the event sampling architecture is effective in FPGA as well. The performance that can be achieved is comparable with the performance of their counterparts that use the clock sampling architecture.

关键词： Time-to-digital converter field programmable gate array Multi-measurement Encoder Measurement throughput

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Simulation and modelling of long term reliability of digital circuits implemented in FPGA

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MICROELECTRONICS RELIABILITY 2018年第Sep.期88-90卷 1130-1134页

作者： Morales, J. D. Aguirre Marc, F. Bensoussan, A. Durier, A. Univ Bordeaux Lab IMS Talence France IRT St Exupery Toulouse France

In this work, we report on the development of a methodology for long term reliability analysis of digital circuits implemented in FPGA. For this, a simulation environment for FPGA has been extended using Python to introduce aging. The aging laws for Look-Up Tables have been integrated by introducing additional variables and equations. They accurately describe the drifts in the propagation time caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms. An analytical model of the failure time of the digital circuit as a function of the clock frequency has been proposed based on the aging law parameters. Finally, the developed methodology has been applied to a CORDIC circuit implemented in FPGA.

关键词： Reliability Modelling Simulation Digital circuits field programmable gate array Negative bias thermal instability Hot Carrier Injection

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Undeviating Adaptive Sheltered Cryptography (UASC) method based low power and high secure cache memory design

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MICROPROCESSORS AND MICROSYSTEMS 2019年 71卷 102876-000页

作者： Sai, R. Vijay Upadhyay, Har Narayan Prabhu, M. Saravanan, S. SASTRA Deemed Univ Sch Comp Thanjavur Tamil Nadu India SASTRA Deemed Univ Sch Elect & Elect Engn Thanjavur Tamil Nadu India

The prerequisite of data security on network has turned out to be more important. Cryptography is a technique to give data privacy, acceptability and integrity. There are such significant number of difficulties to realize cryptography algorithm, for example, execution time, memory requirement, and intention control. In this work, a high secure and low power use of cache memory is implemented for utilizing a new cryptography method specifically named as Undeviating Adaptive Sheltered Cryptography (UASC) algorithm. The outline of the proposed memory has been altered by the expansion of all validation supervisors required by the equipment usage of Advanced Encryption Standard (AES). In addition, UASC has been incorporated into real time application to permit a self-encryption based on full self-rule. Therefore, compared with the conventional design comprising of a crypto-block and an isolated memory, this new method will prompt an imperative decrease of data interactions among the encryption procedure. The proposed work is depicted utilizing Verilog language, synthesized and actualized utilizing Xilinx ISE suite based field programmable gate array (FPGA) devices. Synthesis results demonstrate that the proposed configuration accomplishes higher efficiency than the previous executions by decreasing area while keeping up a moderate throughput/Look UpTable (LUT) ratio. The proposed configuration is additionally more productive as far as power utilization is concerned. As compared with conventional method, the proposed Undeviating Adaptive Sheltered Cryptography achieves low power consumption for 23.02 mu w and execution time is 9.5 s. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Cache memory Encryption Decryption Undeviating Adaptive Sheltered Cryptography field programmable gate array

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A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA

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REVIEW OF SCIENTIFIC INSTRUMENTS 2019年第4期90卷 044706-044706页

作者： Xia, Haojie Cao, Guiping Dong, Ning Hefei Univ Technol Sch Instrument Sci & Optoelect Engn Hefei 230009 Anhui Peoples R China Hefei I Tek OptoElect Co Ltd China Res Ctr High Speed Machine Vis Hefei 230088 Anhui Peoples R China

Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit. Published under license by AIP Publishing.

关键词： Digital circuits Interpolation Time-to-digital converter field programmable gate array Delay lines Electronic circuits

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Design for the system of high-speed data transmission and data pre-processing for synthetic aperture radar imaging based on the system-on-a-programmable-chip

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JOURNAL OF ENGINEERING-JOE 2019年第20期2019卷 6537-6540页

作者： Hu, Shankang Liu, Xiaoning Xie, Yizhuang Hu, Shanqing Li, Bingyi Beijing Inst Technol Sch Informat & Elect Radar Res Lab Beijing 100081 Peoples R China Beijing Inst Technol Beijing Key Lab Embedded Real time Informat Proc Beijing 100081 Peoples R China DFH Satellite Co Ltd Beijing 100081 Peoples R China

For the chirp scaling algorithm of synthetic aperture radar imaging, an efficient transmission of a large volume of data is indispensable. Prior to imaging, there is a requirement for appropriate pre-processing of the echo signal by digital down conversion (DDC). The DDC module has to remove the carrier, having an appropriate filtering processing and down-sampling processing. No matter what imaging mode is chosen, such as the stripmap mode, spotlight mode, and sliding spotlight, the needs of the whole imaging system are matched by setting a series of configurations about this pre-processing module and this transmission module. The system-on-a-programmable-chip constituted by the Advanced RISC Machine and field programmable gate array (FPGA) is the perfect experimental platform to test the performance of this system. Some of the algorithms, which are more feasible for this specific project for pre-processing in Maltab, were transplanted to FPGA using the VHSIC Hardware Description Language for functional verification. Finally, the processing results in Matlab were compared with this system to find the difference. At the same time, the time that elapsed from the 2 GB original data entering the system to the time the processed results were completely returned to the PC was also counted.

关键词： radar imaging synthetic aperture radar system-on-chip field programmable gate array transmission module pre-processing module imaging system spotlight mode stripmap mode down-sampling processing DDC module chirp scaling algorithm system-on-a-programmable-chip synthetic aperture radar imaging data pre-processing high-speed data transmission

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Design and implementation of the MMC simulation system in the heterogeneous FPGA-CPU platform

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JOURNAL OF ENGINEERING-JOE 2019年第16期2019卷 1721-1725页

作者： Li, Xiongfei Mu, Qing Zhang, Xing Xiang, Yinxing Li, Qiao He, Guanghui Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai Peoples R China China Elect Power Res Inst 15 Xiaoyingdonglu Beijing Peoples R China Fujian Elect Power Res Inst Fuzhou Fujian Peoples R China

Real-time simulation of a modular multilevel converter (MMC) plays an important role on the area of large-scale power electronics research. The authors propose a real-time MMC simulation system in a heterogeneous computing platform containing the central processing unit (CPU) and field programmable gate array (FPGA). This system decouples the MMC circuits from the grid based on the alternative circuit equivalent model of the MMC bridge arm. Furthermore, the parallel calculation of the equivalent circuits is achieved when the peripheral circuit is realised on the CPU and the MMC arms are realised on FPGA. In addition, a timing optimisation strategy is discussed to reach the timing target requirement. To validate the MMC simulation system, a case study of a grid with 12 MMC bridges and 640 sub-modules per bridge at 2s time step on Xilinx Virtex-7 XC7VX690T FPGA is simulated in real time. The real-time simulation results demonstrate high accuracy of the simulation system in comparison to the offline simulation of the original system in the electromagnetic transient program and our design is competitive to recent published works.

关键词： field programmable gate arrays voltage-source convertors microprocessor chips equivalent circuits circuit optimisation offline simulation heterogeneous FPGA-CPU platform modular multilevel converter large-scale power electronics research real-time MMC simulation system heterogeneous computing platform field programmable gate array MMC circuits alternative circuit equivalent model MMC bridge arm peripheral circuit timing optimisation strategy timing target requirement central processing unit Xilinx Virtex-7 XC7VX690T FPGA electromagnetic transient program time 2 0 mus

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Research on anti-disturbance performance for servo system with a high dynamic performance velocity acquisition method

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JOURNAL OF ALGORITHMS & COMPUTATIONAL TECHNOLOGY 2018年第2期12卷 110-118页

作者： Hua, Ji Shuang, Wang Shanghai Univ Sch Mechatron Engn & Automat Shanghai 200072 Peoples R China Shandong Univ Technol Sch Elect & Elect Engn Zibo Peoples R China

In order to achieve the requirements of high anti-disturbance and robustness performance for servo system, the acceleration control with disturbance observer is adopted in this paper, where the disturbance observer is used to estimate and compensate the load disturbance. To accomplish the accurate disturbance estimation, higher cut-off frequency of disturbance observer and exact acceleration information are required, where accurate speed estimation is crucial. Thus, a novel velocity acquisition method for servo control system with optical encoder is proposed. At the same time, dynamic error is put forward as a new performance metrics to scientifically explain the dynamic performance of this algorithm. The proposed velocity acquisition method is implemented based on a field programmable gate array. Experimental results show that this novel velocity acquisition method can improve dynamic response performance on the premise of guaranteeing the invariable velocity precision, and at the same time can effectively improve the anti-disturbance and robustness performance of the servo system.

关键词： Velocity acquisition dynamic error anti-disturbance performance robustness control field programmable gate array

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A Review on SEU Mitigation Techniques for FPGA Configuration Memory

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IETE TECHNICAL REVIEW 2018年第2期35卷 157-168页

作者： Nidhin, T. S. Bhattacharyya, Anindya Behera, R. P. Jayanthi, T. Indira Gandhi Ctr Atom Res Homi Bhabha Natl Inst Kalpakkam Tamil Nadu India

Single event upset (SEU) has become one of the major threats to dependable application development targeted at safety systems in field programmable gate arrays (FPGAs). This article briefly reviews the mitigation techniques for SEUs in the configuration memory of SRAM-based FPGAs, as the configuration memory is highly susceptible to SEUs. Various reconfiguration methods are reviewed and the main focus is given to partial reconfiguration with error correction codes and scrubbing. It also covers the algorithmic and architectural changes which prevent or mitigates SEUs in the configuration memory bits dedicated for routing resources and logic resources. The major techniques are compared based on their SEU mitigation capability, area overhead, and delay.

关键词： Configuration memory Error correction codes Fault tolerance field programmable gate array Look-up-tables Partial reconfiguration Routing errors Single event upsets Scrubbing

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Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

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JOURNAL OF ENGINEERING-JOE 2019年第21期2019卷 7424-7427页

作者： Wei, Xin Xie, Yi Z. Xie, Yu Chen, He Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

关键词： field programmable gate arrays fault tolerant computing fast Fourier transforms redundancy radiation hardening (electronics) microprocessor chips reconfiguration time multipath delay feedback FFT controller dynamic partial reconfiguration scheme fault-tolerant FFT processor field programmable gate array logical resources storage resources dynamic partial reconfiguration technique fast Fourier transform FFT processor novel FPGA scrubbing framework high-energy particles triple modular redundancy scheme DPR controller blind scrubbing Xilinx PRC IP single event upset

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