This paper explains the design and implementation of Perturb and Observe Maximum Power Point Tracking Algorithm combined with the Closed Loop Digital PI control algorithm to generate the Digital Pulse Width Modulation...
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This paper explains the design and implementation of Perturb and Observe Maximum Power Point Tracking Algorithm combined with the Closed Loop Digital PI control algorithm to generate the Digital Pulse Width Modulation using Xilinx Spartan 3A DSP field programmable gate array for regulating the load voltage of DC-DC buck converter. And also concentrates on the methods for generation of DPWM techniques say Delay line based Digital Pulse Width Modulation and Hybrid based Digital Pulse Width Modulation with the 210 bit resolution. All the algorithms are developed by VHSIC Hardware Description Language coding and are implemented using Xilinx ISE 12.1 tool. The hardware results validate the satisfactory voltage regulation of PV system under continuous changing weather condition. The Hybrid based Digital Pulse Width Modulation seems to have better time transient response than the Delay line based Digital Pulse Width Modulation. (c) 2017 Elsevier Ltd. All rights reserved.
In this paper a FPGA-based dynamic model of a three-phase Vienna Rectifier with unity power factor operations has been developed addressing applications as stationary chargers for electric vehicle or telecom rectifier...
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ISBN:
(纸本)9781538647592
In this paper a FPGA-based dynamic model of a three-phase Vienna Rectifier with unity power factor operations has been developed addressing applications as stationary chargers for electric vehicle or telecom rectifiers. Such a model has been implemented to be used in a Hardware In the Loop (HIL) system where the power converter has been replaced with an embedded system based on a FPGA board. The proposed system has been designed to test converter control algorithms in a fast and safe way. The proposed solution exploits an environment software platform with a high level abstraction, obtaining a good trade-off between accuracy and hardware resources, also allowing a faster prototyping procedure. The HIL implementation has been compared with that of the experimental rig, confirming a good agreement in terms of accuracy and dynamic behavior.
Specialists in embedded systems software are leading force of almost every consumer electronics project. Universities all over the world offer different teaching programs of embedded software engineering to satisfy hu...
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ISBN:
(纸本)9781538646151
Specialists in embedded systems software are leading force of almost every consumer electronics project. Universities all over the world offer different teaching programs of embedded software engineering to satisfy huge demand in software developers. The article presents the model of a specialist in embedded systems, university graduates competence requirements, a set of disciplines and teaching methods. New "Software Engineering" curriculum project is proposed ("Embedded Software" profile), which is based on achievements of the world leading universities, ACM Curricula Recommendations and analysis of embedded systems market surveys.
In this paper, a real-time field programmable gate array (FPGA) implementation of the Echo State Network (ESN) architecture of Recurrent Neural Network (RNN) training has been presented, which computes the output weig...
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ISBN:
(纸本)9781538672266
In this paper, a real-time field programmable gate array (FPGA) implementation of the Echo State Network (ESN) architecture of Recurrent Neural Network (RNN) training has been presented, which computes the output weights of the particular Reservoir Computing (RC) architecture in FPGA in real-time. The proposed implementation is in strict conformance with the RC theory. The four parts of the ESN architecture, which are the input block, reservoir block, output block, and weight training block, were all constructed in FPGA. The training of the ESN was completed in real-time and its performance verified through implementation in Altera FPGA. The error rate is 8% in sinusoidal pattern recognition task, which showed that the proposed real-time FPGA implementation of the ESN can realize short-time memory and recognize various periodicities of input signals after training. The proposed method shows the massive parallel processing capability of the RC.
Modern commercial EDA tools provide end users with a framework for application specific customizations through a general-purpose programming language interface to an underlying circuit object model Xilinx Vivado expos...
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ISBN:
(纸本)9781538665572
Modern commercial EDA tools provide end users with a framework for application specific customizations through a general-purpose programming language interface to an underlying circuit object model Xilinx Vivado exposes that information through Tcl. This work demonstrates an implementation of a static hardware detection algorithm utilizing this interface of Vivado.
This paper proposes the Predictive sliding mode controller which is based on Adaptive Neuro-fuzzy Inference system. In this Predictive current VSS control strategy introduced to control the voltage source inverter as ...
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ISBN:
(纸本)9781538625996
This paper proposes the Predictive sliding mode controller which is based on Adaptive Neuro-fuzzy Inference system. In this Predictive current VSS control strategy introduced to control the voltage source inverter as a system with the finite number of possible state and selecting over each sampling period and the voltage vector that minimizes the quadratic cost function. Common DSP solutions are rarely used as compared to FPGA hardware and main advantage of this method is that all the logic is executed continuously and simultaneously. This ANFIS controller introduced for considering the voltage source inverter with a finite number of possible states and selecting that possible state speed can be controlled. Brushless ac motor can provide good transient response and this proposed control method is applicable for all types of ac loads as well as ac motors. The result analyzed by design switching based current controller for a three phase load driven by a power inverter and speed controller for BLAC motor by using Xilinx Spartan 3E FPGA.
Authenticated ciphers are vulnerable to side-channel attacks, including differential power analysis (DPA). Test Vector Leakage Assessment (TVLA) using Welch's t-test has been used to verify improved resistance of ...
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ISBN:
(纸本)9781538647318
Authenticated ciphers are vulnerable to side-channel attacks, including differential power analysis (DPA). Test Vector Leakage Assessment (TVLA) using Welch's t-test has been used to verify improved resistance of block ciphers to DPA after application of countermeasures. However, extension of this methodology to authenticated ciphers is non-trivial, since this requires additional input and output conditions, complex interfaces, and long test vectors interlaced with protocol necessary to describe authenticated cipher operations. In this research we augment an existing side-channel analysis architecture (FOBOS) with TVLA for authenticated ciphers. We use this capability to show that implementations in the Spartan-6 FPGA of the CAESAR Round 3 candidates ACORN, ASCON, CLOC (AES and TWINE), SILC (AES, PRESENT, and LED), JAMBU (AES and SIMON), and Ketje Jr., as well as AES-GCM, are potentially vulnerable to 1st order DPA. We then implement versions of the above ciphers, protected against 1st order DPA, using threshold implementations. TVLA is used to verify improved resistance to 1st order DPA of the protected cipher implementations. Finally, we benchmark unprotected and protected cipher implementations in the Spartan-6 FPGA, and compare the costs of 1st order DPA protection in terms of area, frequency, throughput, throughput-to-area (TP/A) ratio, power, and energy per bit. Our results show that ACORN is the most energy efficient, has the lowest area (in LUTs), and has the highest TP/A ratio of DPA-resistant implementations. However, Ketje Jr. has the highest throughput.
Dynamic Partial Reconfiguration (DPR) has been used extensively over the past few years allowing reconfiguration of field programmable gate array (FPGA) during run time. With the aid of DPR, multi-standard Software De...
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ISBN:
(纸本)9781538676813
Dynamic Partial Reconfiguration (DPR) has been used extensively over the past few years allowing reconfiguration of field programmable gate array (FPGA) during run time. With the aid of DPR, multi-standard Software Defined Radio (SDR) system can be implemented in order to save power and area extensively. In this paper, SDR is implemented using five wireless communication systems: Bluetooth, Wi-Fi, 2G, 3G, and LTE on the same reconfigurable hardware. A test environment is established to measure the effectiveness of the new technique using Zynq-7000. A comparison is performed for the system total area and power consumption with and without DPR. This work achieves reduction of area and power by 10.19% and 76.71% respectively using DPR with an average switching time of 3.49 ms.
Considering the capacitor voltage balance (CVB) in modular multilevel converter (MMC), classical complete sorting algorithms, especially used in MMC with a large number of submodules (SMs), usually result in too much ...
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ISBN:
(纸本)9781538611807
Considering the capacitor voltage balance (CVB) in modular multilevel converter (MMC), classical complete sorting algorithms, especially used in MMC with a large number of submodules (SMs), usually result in too much computational load and resource consumption. A fast selection algorithm based on binary numbers is proposed to achieve CVB in MMC. The algorithm needs not fully sorting all the numbers, and the complexity of it rapidly decreases by using a binary division mechanism. These properties make the proposed algorithm fast and resource-saving, and easily being implemented in many types of microcontrollers. Taking into account the needs of engineering applications, some techniques used to improve algorithm speed and reduce Filed programmablegatearray (FPGA) resource consumption are discussed when implementing algorithms in FPGA. The required resources and execution time of the proposed algorithm is evaluated, and a comparison between the proposed algorithm and some other sorting algorithms is used to verify the conclusions.
This paper proposes an FPGA based four quadrants operation of Brushless DC (BLDC) motor control using FPGA-SPARTAN-6 device. This control practice for four-quadrant operation identifies the rotor rotating constraint a...
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ISBN:
(数字)9789811319365
ISBN:
(纸本)9789811319365;9789811319358
This paper proposes an FPGA based four quadrants operation of Brushless DC (BLDC) motor control using FPGA-SPARTAN-6 device. This control practice for four-quadrant operation identifies the rotor rotating constraint and fluctuations the quadrant of operation accordingly. The motor controlling methodology designed to work in all the four quadrants without any deprivation of power. A low-cost, easy to use improvement and assessment platform for Spartan-6 FPGA designs. This paper presents modern BLDC motor drives with an importance on FPGA Spartan-6 control of these motors. The effectiveness of the proposed technique established complete experimental results.
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