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检索条件"主题词=Field Programmable Gate array"

共 1339 条记录，以下是571-580 订阅

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Memory-Efficient Architecture for Accelerating Generative Networks on FPGA 17

Memory-Efficient Architecture for Accelerating Generative Ne...

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17th International Conference on field-programmable Technology (FPT)

作者： Liu, Shuanglong Zeng, Chenglong Fan, Hongxiang Ng, Ho-Cheung Meng, Jiuxi Que, Zhiqiang Niu, Xinyu Luk, Wayne Imperial Coll London Dept Comp London England Tianjin Univ Sch Microelect Tianjin Peoples R China Corerain Technol Ltd Shenzhen Peoples R China

ISBN: (纸本)9781728102139

Generative adversarial networks (GANs) are a class of artificial intelligence algorithms used in unsupervised machine learning, implemented by a system of two neural networks: a generative network (generator) and a discriminative network (discriminator). These two networks compete with each other to perform better at their respective tasks. The generator is typically a deconvolutional neural network and the discriminator is a convolutional neural network (CNN). Deconvolution performs a fundamentally new type of mathematical operation which differs from convolution. While the FPGA-based CNN accelerators have been widely studied in prior work, the acceleration of deconvolutional networks on FPGA is rarely explored. This paper proposes a novel parametrized deconvolutional architecture based on an FPGA-friendly method, in contrast to the transposed convolution implementation in CPUs and GPUs. Hardware design templates which map this architecture to FPGAs are provided with configurable deconvolutional layer parameters. Furthermore, a memory-efficient architecture with a new tiling method is proposed to accelerate the generator of GANs, by storing all intermediate data in on-chip memories to significantly reduce off-chip data transfers. The performance of the proposed accelerator is evaluated using a variety of GANs on a Xilinx Zynq 706 board, which shows 2.3x higher speed and 8.2x offchip memory access reduction than an optimized Vanilla FPGA design. Compared to the respective implementations on CPUs and GPUs, the achieved improvements are in the range of 30x92x in speed over an Intel 8-core i7-950 CPU, and 8x-108x in terms of Performance-per-Watt over an NVIDIA Titan X GPU.

关键词： Deconvolution field programmable gate array Generative adversarial networks (GANs) Hardware Acceleration

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Efficient Architecture for Implementation of Hermite Interpolation on FPGA 12

Efficient Architecture for Implementation of Hermite Interpo...

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12th Conference on Design and Architectures for Signal and Image Processing (DASIP)

作者： George, Gibin Chacko Moitra, Abhishek Caculo, Sriyash Prince, A. Amalin BITS Pilani Dept EEE Goa Campus Pilani Goa India

ISBN: (纸本)9781538682371

Interpolation is widely used for a number of applications. For instance, it is used to generate geometric models, path trajectories and various applications of signal processing including data compression. Traditionally, software implementation of interpolation is carried out using a General Purpose Processor (GPP) or Digital Signal Processor (DSP). field programmable gate arrays (FPGAs) however, offer a more customizable and faster solution. This paper presents a hardware accelerator architecture for Hermite Interpolation on FPGA. Cubic Hermite interpolation, specifically Catmull-Rom spline is preferred over other techniques due to ease of computation and local control which makes it an ideal method to implement very low-complexity architecture. A data flow approach has been used as it provides high throughput for intensive data processing. Additionally, the efficiency of computation has been improved by implementing a pipelined architecture. The proposed architecture has been implemented on Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 using the Xilinx Vivado Design Suite. Results obtained from fixed point FPGA implementation were found to have high fidelity with floating point MATLAB simulations. Root Mean Squared Error (RMSE) of 1.704x10(-4) and a correlation of 99.84% was obtained.

关键词： field programmable gate array Interpolation Digital Signal Processing Hermite Interpolation Catmull-Rom Spline Data Flow Architecture

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Design of an Adaptive Sinusoid Interference Cancellation Algorithm using FPGA and Its Performance Evaluation 3

Design of an Adaptive Sinusoid Interference Cancellation Alg...

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3rd IEEE Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)

作者： He, Kuihua Zhou, Guofei Zhou, Xiaobo Beijing Jiaotong Univ Sch Elect & Informat Engn Beijing Peoples R China Minist Publ Secur PRC Res Inst 1 Beijing Peoples R China

ISBN: (纸本)9781538645093

The sinusoid interference of continuous wave radar would drown the echo signal of targets and restricts the improvement of performance. An adaptive notch filter based on fast recursive-least-squares (FRLS) is proposed to eliminate sinusoid interference. Compared with conventional RLS algorithm, the FRLS reduces more than half of computation by making a reasonable approximation. The new strategy proposed uses a numerical control oscillator (NCO) based on hardware friendly CORDIC to generate two orthogonal reference signals. The developed architecture was described in Verilog HDL and synthesized to FPGA. Synthesis results demonstrate that the proposed method can quickly track the amplitude and phase of sinusoid interference within 0.5 ms.

关键词： field programmable gate array adaptive notch filter recursive-least-squares

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Comparison of Accelerator Coherency Port (ACP) and High Performance Port (HP) for Data Transfer in DDR Memory Using Xilinx ZYNQ SoC 2nd

Comparison of Accelerator Coherency Port (ACP) and High Perf...

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2nd International Conference on Information and Communication Technology for Intelligent Systems (ICTIS)

作者： Nayak, Rikin J. Chavda, Jaiminkumar B. Charotar Univ Sci & Technol Chandubhai S Patel Inst Technol E&C Dept Changa 388421 Gujarat India Charotar Univ Sci & Technol Chandubhai S Patel Inst Technol IT Dept Changa 388421 Gujarat India

ISBN: (纸本)9783319636733;9783319636726

ZYNQ 7000 Embedded Processing Platform SOC is chips includes ARM dual core A9-MPCore Processor Processing System-(PS-Microprocessor) along with Xilinx programmable Logic (PL)-Artix 7 FPGA on a single die. ZYNQ SoC provides the high performance and computing throughput at low power using PS along with the flexibility of PL. ZYNQ SoC incorporates independent interfaces for communication of data control signals between PL and PS in various configurations to access the system resources. This paper describes the performance evaluation of such interfaces in terms of resource utilization and power consumption. Here, in this paper, data transfer from PL to PS using low speed AXI GP port and high speed bus like AXI HP port and ACP (Accelerator Coherency) port is discussed. The paper includes design, implementation and testing results on Zynq-7000 SoC based Avnet Zed board.

关键词： field programmable gate array ZYNQ-7000 SoC System on chip High speed data acquisition

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programmable System on Chip implementation of a Principal Component Analysis for preprocessing of multispectral image data acquired with filter wheel cameras 24

Programmable System on Chip implementation of a Principal Co...

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24th SPIE Conference on Algorithms and Technologies for Multispectral, Hyperspectral, and Ultraspectral Imagery

作者： Schellhorn, Mathias Fuetterer, Richard Rosenberger, Maik Notni, Gunther Ilmenau Univ Technol Fac Mech Engn Dept Qual Assurance & Ind Image Proc POB 10 05 65 D-98684 Ilmenau Germany

ISBN: (数字)9781510618008

ISBN: (纸本)9781510618008

The acceleration of the acquisition of spectral images and their processing is important for the acceptance of these measurement methods in quality assurance and inspection. A frequently used preprocessing step is the Principal Component Analysis (PCA). It is used in variations, for example, for segmentation, spectral decomposition or data compression. The presented implementation calculates the PCA for the 12 spectral image channels of a filter wheel camera parallel to image acquisition. This includes the determination of the covariance matrix, the calculation of the main components and the transformation of the data. The parallel processing during the sequential imaging acquisition is performed on a System-on-a-programmable-chip (SoPC) Xilinx Zynq-7000 directly within the camera. The algorithm is partitioned into hard and software components and implemented in the field programmable gate array (FPGA) fabric as well as the ARM processor core firmware of the SoPC. In order to ensure the steps of the image acquisition chain in addition to the calculation, the system was implemented as an asymmetric multiprocessing system (AMP) with individual processors. For additional acceleration under static conditions (e.g. continuous testing in the manufacturing process), the feature vector can be stored as a calibration value. The calculation is reduced to the transformation of the data.

关键词： spectral imaging Principal Component Analysis field programmable gate array system-on-a-programmable-chip filter wheel camera

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Chip Design for Turbo Encoder Module for In-Vehicle System 8

Chip Design for Turbo Encoder Module for In-Vehicle System

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8th IEEE Annual Computing and Communication Workshop and Conference (CCWC)

作者： Nader, Majeed Li, Yunrui Liu, John Wayne State Univ Elect & Comp Engn Detroit MI 48202 USA

ISBN: (纸本)9781538646496

This paper studies design and implementation of the Turbo encoder to be an embedded module in the in-vehicle system (IVS) chip. field programmable gate array (FPGA) is employed to develop the Turbo encoder module. Both serial and parallel computations for the encoding technique are studied. The two design methods are presented and analyzed. Developing the parallel computation method, it is shown that both chip size and processing time are improved. The logic utilization is enhanced by 73% and the processing time is reduced by 58%. The Turbo encoder module is designed, simulated, and synthesized using Xilinx tools. Xilinx Zynq-7000 is employed as an FPGA device to implement the developed module. The Turbo encoder module is designed to be a part of the IVS chip on a single programmable device.

关键词： Turbo encoder module field programmable gate array emergency call in-vehicle system chip

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TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs

TURTLE: A Low-Cost Fault Injection Platform for SRAM-based F...

引用

International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Corbin Thurlow Hayden Rowberry Michael Wirthlin NSF Center for Space High-performance and Resilient Computing (SHREC) Brigham Young University Provo Utah USA

ISBN: (纸本)9781728119588

This paper presents the TURTLE fault injection platform for inserting faults into SRAM FPGAs. The TURTLE system is designed to gather significant fault injection data to test and validate radiation-induced single-event upset (SEU) mitigation techniques for FPGAs. The TURTLE is a low-cost fault injection platform that emulates upsets within the configuration memory (CRAM) of an FPGA through partial reconfiguration. This work successfully implemented the proposed architecture and performed several successful fault injection campaigns on multiple designs and SEU mitigation techniques. Results in this paper show large amounts of data collected from a fault injection campaign used to validate the PCMF SEU mitigation technique. Over 170 million injections were performed using the TURTLE for this campaign.

关键词： field programmable gate array Fault injection SEU Mitigation field programmable gate arrays Single event upsets faults Injections Upset Platform

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Behavior of a Hippocampal Spiking Network and FPGA Implementation

Behavior of a Hippocampal Spiking Network and FPGA Implement...

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第三十八届中国控制会议

作者： Jingyi Hao Xinyu Hao Jiang Wang Shuangming Yang Bin Deng Haitao Yu School of Electrical and Information Engineering Tianjin University

The hippocampus in human brain is responsible for memory processing and tasks learning, which has long been one of the main interests of many researchers. In this paper, a spiking neural network of the hippocampus is realized based on a designed task. In the task, the model rat firstly gets familiar with the environment and finds item in one of the pots and finally gets a reward for making the correct response. Through the network, the feature of the hippocampal neurons can be simulated in software successfully. The three-layer network was built based on the spike-timing dependent synaptic plasticity and the synaptic weights will be modified between layers during task which can finally achieve the memory-related behavior of the model rat. Besides software realization, we also utilize field programmable gate array(FPGA) to reproduce the characteristics of the network in real time. The results show that the spiking neural network of the hippocampus can mimic the memory-related behavior of the model rat.

关键词： Hippocampus spiking neural network memory-related behavior field programmable gate array

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Optimization of FPGA-based LDPC decoder using high-level synthesis 18

Optimization of FPGA-based LDPC decoder using high-level syn...

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4th International Conference on Communication and Information Processing (ICCIP)

作者： Choi, Geon Park, Kyeong-Bin Chung, Ki-Seok Hanyang Univ 222 Wangsimni Ro Seoul South Korea

ISBN: (纸本)9781450365345

Low Density Parity Check (LDPC) codes are widely used in various communication and storage systems due to outstanding error correcting capability. In this paper, we present a field programmable gate array (FPGA) implementation of the LDPC decoder using High-Level Synthesis (HLS). Because HLS can synthesize a hardware implementation from a high-level description, it is very effective in reducing design time, and in exploring various design alternatives. One of the biggest advantages of FPGAs is flexibility, and therefore, HLS for FPGAs is widely adopted as a good hardware synthesis method. In this paper, we describe an LDPC decoder in high level language, and a HLS tool called SDSoC is used to synthesize the decoder. The proposed design is a serial LDPC decoder that requires smaller amount on hardware resource and power consumption than the conventional design. The major drawback of a serial decoder is slow speed. To overcome such drawback, optimization techniques such as array partitioning, loop unrolling, pipelining methods and fixed-point conversion are applied. With the application of these techniques, the decoding speed of the proposed implementation is 8.11 times and 2.79 times faster than that of a non-optimized implementation and that of a software-based LDPC decoder, respectively.

关键词： Error Correcting Code field programmable gate array High Level Synthesis Low Density Parity Check SDSoC

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Simultaneous Partitioning and Signals Grouping for Time-Division Multiplexing in 2.5D FPGA-Based Systems 18

Simultaneous Partitioning and Signals Grouping for Time-Divi...

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37th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Chen, Shih-Chun Sun, Richard Chang, Yao-Wen Natl Taiwan Univ Grad Inst Elect Engn Taipei 106 Taiwan Synopsys Inc Mountain View CA USA Natl Taiwan Univ Dept Elect Engn Taipei 106 Taiwan

ISBN: (纸本)9781450359504

The 2.5D FPGA is a promising technology to accommodate a large design in one FPGA chip, but the limited number of inter-die connections in a 2.5D FPGA may cause routing failures. To resolve the failures, input/output time-division multiplexing is adopted by grouping cross-die signals to go through one routing channel with a timing penalty after netlist partitioning. However, grouping signals after partitioning might lead to a suboptimal solution. Consequently, it is desirable to consider simultaneous partitioning and signal grouping although the optimization objectives of partitioning and grouping are different, and the time complexity of such simultaneous optimization is usually high. In this paper, we propose a simultaneous partitioning and grouping algorithm that can not only integrate the two objectives smoothly, but also reduce the time complexity to linear time per partitioning iteration. Experimental results show that our proposed algorithm outperforms the state-of-the-arts flow in both cross-die signal timing criticality and system-clock periods.

关键词： field programmable gate array Partitioning Physical Design Signal Grouping Time-Division Multiplexing

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