检索结果-内蒙古大学图书馆

作者： Enyi Wang Dehui Qiu Information and Engineering College Capital Normal University

Aiming at the problem of high power consumption and slow operation speed of neural network in embedded system, this paper presents an automatic design method of convolutional neural network(CNN) accelerator based on field programmable gate array(FPGA) to meet the requirements of embedded terminal for operation performance and power consumption. Firstly, in order to reduce the storage resources of the FPGA and the time required for network computing, the weight quantization method is used to convert network parameters from floating-point data to binary data. Secondly, in order to improve the speed and throughput of the whole system, coarse-grained and fine-grained parallel computing optimization methods are used. In this paper, the above acceleration scheme will be applied to the scene of unmanned aerial vehicle(UAV) object detection. The test results shows that the power consumption of the system is 2.38 W and the calculated power consumption ratio is 29.3 GOPS/W. Compared with the work of related literature in recent years, the proposed scheme can provide higher speed and efficiency. The experimental results show that the accuracy of the IOU is 21% and the speed is 7 FPS.

关键词： Convolutional Neural Network field programmable gate array Weight quantization Parallel computing Object detection

来源：评论

学校读者我要写书评

暂无评论

FPGA Performance Optimization Plan for High Power Conversion 1

引用

2nd International Conference on Soft Computing Systems (ICSCS)

作者： Muthukumar, P. Kanthan, Padma Suresh Lekshmi Immanuel, T. Baldwin Eswaramoorthy, K. PVP Siddhartha Inst Technol Dept Elect & Elect Engn Vijayawada 520007 India Baselios Mathew II Coll Engn Dept Elect & Elect Engn Sasthamkotta 690521 Kerala India AMET Deemed Univ Dept Elect & Elect Engn Chennai 603112 Tamil Nadu India Anna Univ Dept Elect & Elect Engn Chennai 600025 Tamil Nadu India

ISBN: (数字)9789811319365

ISBN: (纸本)9789811319365;9789811319358

One of the major part of any power converter system is a blistering implementation of PWM algorithm for high power conversion. It must fulfil both requirements of power converter hardware topology and computing power necessary for control algorithm implementation. The emergence of multi-million-gate FPGAs with large on-chip RAMs and a processor cores sets a new trend in the design of FPGAs which are exceedingly used to generate the PWM in the area of power electronics. Of late, more and more large complex designs are getting realized using FPGAs, because of less NRE cost and shorter development time. The share of programmable Logic Devices (PLD), especially FPGAs, in the semiconductor logic market is tremendously growing year-on-year. This calls for an increased controllability of designs, in terms of meeting both area and timing performance, to really derive the perceived benefits. The recent strides in FPGA technology favour the realization of large high-speed designs, which were only possible in an ASIC, in FPGA now. However the routing delay being still unpredictable and the pronounced nature of routing delay over logic delay, in today's FPGAs impedes the goal of early timing convergence. This paper introduces the few techniques for controlling the design area/ time right from architecture stage and the technique can adopt for any FPGA based design applications including the high power conversion. This paper also describes the trade off between Area, speed and power of the optimization techniques.

关键词： field programmable gate array programmable Logic Devices Application specific integrated circuits Flip flops Optimization Register transfer logic Block ram Embedded array block Configurable logic blocks

来源：评论

学校读者我要写书评

暂无评论

VGA Application in Text Display Using FPGA 2nd

VGA Application in Text Display Using FPGA

引用

2nd International Conference on Intelligent Communication, Control and Devices (ICICCD)

作者： Mishra, Akarsha Kumar, Adesh Parihar, Rakshita UPES Dehra Dun Uttarakhand India UPES Dept Elect Instrumentat & Control Engn Dehra Dun 248007 Uttarakhand India

ISBN: (纸本)9789811059032;9789811059025

This research paper presents the idea of designing and implementing the VGA applications on FPGA. The goal of the first application here is to display a four-bit digit on a VGA screen, and the second application focuses on displaying a 32-bit text on the screen. VGA plays an important role in displaying the data on the screen. VGA cable is connected to the FPGA board easily since a VGA connector is provided on the board. The module is designed by programming of code in VHDL on Xilinx ISE 14.7 software. The synthesis is done with the help of Spartan 3E FPGA which estimate the supporting frame of 50 MHz.

关键词： field programmable gate array Very high speed hardware description language Video graphics array

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of Multi-carriers PWM Technique for Modular Multi-level Inverter

FPGA Implementation of Multi-carriers PWM Technique for Modu...

引用

International Conference on Applied Smart Systems (ICASS)

作者： Atoui, Elmoatez Billah Mesbah, Tarek Atoui, Hamza Badji Mokhtar Univ Annaba Dept Elect Engn Annaba 23000 Algeria Tebessa Univ Dept Elect Engn Tebessa Algeria

ISBN: (纸本)9781538668665

The present paper proposes the implementation of multi-carriers PWM technique based-on field programmable gate array (FPGA) for Modular Multilevel Converter (MMC). Focus-on level shifted PWM, the Phase Disposition PWM (PD-PWM) has been analyzed for 3-phase 5-level Modular Multilevel Inverter (MMI). A complete digital controller of PD-PWM technique was designed using the Hardware Description Language (VHDL). The developed controller contains four principal blocks;programmable clock divider block, ROM phases generator block, up/down counter block for carriers generator and combinatorial block based-on comparators in order to generate the gate signals of each phase with dead time. Xilinx ISE and Modelsim are used as simulation software in order to verify and synthesize the behavioral and correctness of developed controller which are achieved. After implementation on Digilent Atlys FPGA board, the experimental gate signals waveforms are obtained via a digital oscilloscope.

关键词： Modular Multilevel Inverter field programmable gate array VSC-HVDC system Renewable Energy

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of Real-Time Soldier Activity Detection based on Neural Network Classifier in Smart Military Suit

FPGA Implementation of Real-Time Soldier Activity Detection ...

引用

IEEE Bombay Section Signature Conference (IBSSC)

作者： Nikhil B. Gaikwad Avinash G. Keskar Varun Tiwari NC Shivaprakash Electronics and Communication Department Visvesvaraya National Institute of Technology (VNIT) Nagpur India Department of Instrumentation and Applied Physics Indian Institute of Science (IISc) C V Raman Ave Bengaluru India

ISBN: (纸本)9781538674765

The wearable technology carries sufficient potential to incorporate smartness into working of the military workforces like the Military Control Unit, Medical Responders, Backup Unit and War Strategist. The proposed work focuses on real-time soldier activity detection, which is essential for the operation of the smart military suit. The customized Artificial Neural Network (ANN) IP core is developed for the soldier activity classification, which is an integral component of suit gateway design. The multilayer perceptron (7-5-4) classification algorithm is implemented on the low-cost (99$) FPGA evaluation platform by using Xilinx vivado and system generator development tools. The training (70%) and testing (30%) of this ANN design is performed on the UCI human activity dataset. The LabVIEW GUI and IP test design completed the hardware testing of this IP. The presented ANN IP is able to achieve 98.5% classification accuracy by utilizing minimal FPGA (Artix-7 xc7a35t) resources. The implemented ANN design requires only 285 nanoseconds for a classification and consumes 103 milliwatts of dynamic power. The system's accuracy at different development levels is also studied in this work.

关键词： Smart military suit Soldier activity detection Artificial neural network Smart sensor gateway Network centric warfare field programmable gate array field programmable gate arrays Artificial neural networks Soldiers Activity Detection Military Personnel Hardware Test brightness EIS IMPLEMENTATION PLANS Bayesian classifier Sorting algorithm

来源：评论

学校读者我要写书评

暂无评论

An area-efficient low-power SCM topology for high performance network-on Chip (NoC) architecture using an optimized routing design

引用

CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2019年第14期31卷 e4760-e4760页

作者： Poovendran, R. Sumathi, S. Adhiyamaan Coll Engn Dept ECE Hosur India

The incorporation of network-on-Chip with communication delivers a strengthening solution to the rising complexity and problems in system-on-chip. Here, mesh topology is shortly connected, utilizing the symmetric properties of the network, and is introduced. In addition, 4x4-Router Architecture-Carry Select Adder (4x4-RA-CSLA) method is proposed to improve the function of the Router Architecture (RA) in the network. These features make the system achieve efficient architecture in terms of lower area and power for the interconnection of network scenarios. This new architecture is debugged using ModelSim with Verilog code. The experimental result shows improvement in area and power.

关键词： application specified integrated chip diametrical mesh field programmable gate array network-on-chip 4x4-Router Architecture-Carry Select Adder

来源：评论

学校读者我要写书评

暂无评论

A Scalable FPGA Design for Cloud N-Body Simulation 29

A Scalable FPGA Design for Cloud N-Body Simulation

引用

29th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Del Sozzo, Emanuele Rabozzi, Marco Di Tucci, Lorenzo Sciuto, Donatella Santambrogio, Marco D. Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy

ISBN: (纸本)9781538674796

The N-Body simulation process describes the evolution of a system of forces composed of N bodies, which may represent celestial objects, molecules, and so on. The most accurate algorithm for N-Body simulation, the All-Pairs method, is particularly compute intensive and software implementations on CPUs are inefficient in terms of performance and power consumption. An implementation on a hardware accelerator, such as an FPGA, would benefits in both these terms, exploiting a parallel execution at a relative low power profile. Moreover, it would also benefit faster methods with lower computational complexity, since many of them rely on the All-Pairs approach to approximate the calculation of forces. This work proposes a highly scalable, power efficient and high performance hardware architecture for the N-Body All-Pairs simulation problem. Our final implementation is able to scale up to systems with an arbitrary number of bodies thanks to a tiling approach that allows performance in the order of 13,441 MPairs/s, outperforming state of the art implementations on FPGA in terms of both pure performance, as well as performance per watt ratio. Finally, our design results to be more power efficient than Grape-8 ASIC.

关键词： N-Body Simulation field programmable gate array Hardware acceleration Semi-Dataflow Architecture AWS Amazon F1 Cloud computing

来源：评论

学校读者我要写书评

暂无评论

Design of a Multichannel Time Interval Measurement Interface Box

Design of a Multichannel Time Interval Measurement Interface...

引用

作者： Don, M. L Pugh, K. E Kline, B. J Hallameyer, J. M CCDC Army Research Laboratory Aberdeen Proving Ground United States

Precise time interval measurement is required for a number of applications including clock stability analysis, time-of-flight measurements, and particle physics. Commercial time interval measurement devices can achieve picosecond resolution but are expensive, especially for multichannel applications. In previous research, the US Army Combat Capabilities Development Command Army Research Laboratory demonstrated 10-ns resolution on 10 channels using a low-cost field-programmable gate array (FPGA) suitable for pulse-per-second monitoring. This technical note details the design of an interface box for this FPGA device, enabling practical time interval measurement with a variety of input signals. The purpose of this note is twofold: 1) to document the interface box to allow for easy use and future modifications and 2) to provide a reference to facilitate the construction of other interface units, including design advice and lessons learned.

关键词： field programmable gate array Time intervals Measurement Monitoring Time interval measurement field-programmable gate array Pulse per second Test and measurement Electronic interface

来源：评论

学校读者我要写书评

暂无评论

AN EXPLORATION OF ERROR-CORRECTING CODES FOR USE IN NOISE-PRONE SATELLITE ENVIRONMENTS

AN EXPLORATION OF ERROR-CORRECTING CODES FOR USE IN NOISE-PR...

引用

作者： Min W. Kang Air Force Institute of Technology

学位级别：硕士

Satellites are crucial for the modern world to function properly as they provide Global Navigation Satellite System (GNSS) and global communication. However, the data that is stored on these satellites can be corrupted by the radiation found in space, and its bits can be improperly flipped. In the past, Forward Error Correction (FEC) algorithms were selected based on their strength and implemented to correct these bit flips back to their original values. This thesis seeks to determine if the strength of the FEC algorithms Reed Solomon (RS) code and Reed Solomon Product Code (RSPC) directly translates to their effectiveness. These algorithms were coded and tested in Matrix Laboratory (MATLAB) and on a field programmable gate array (FPGA) under controlled parameters, including the data set sizes, number of bit flips introduced, and the distribution of the bit flips within the data set. From the experiment's results, these other factors significantly influenced the effectiveness of the algorithms as well. Knowing what factors influence the algorithm's effectiveness enable better decision making as to which FEC algorithm to use for a given set of circumstances. The RS codes should be used if the size of the data set is small enough for a single-instance RS code and the range of expected bit flips is narrow and lower than the code's correctable limit. If the data set is large or the range of expected bit flips varies widely and surpasses the RS code's correctable limit, the RSPC should be used for a higher overall success rate in exchange for a lower number of bit flips with a 100% correction rate.

关键词： Forward Error Correction Reed Solomon Codes Reed Solomon Product Codes MATLAB field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

A non-contact infection screening system using medical radar and Linux-embedded FPGA: Implementation and preliminary validation

引用

Informatics in Medicine Unlocked 2019年 16卷 100225页

作者： Nguyen, Cuong V. Le Quang, Truong Vu, Trung Nguyen Le Thi, Hoi Van, Kinh Nguyen Trong, Thanh Han Trong, Tuan Do Sun, Guanghao Ishibashi, Koichiro School of Electronics and Telecommunications Hanoi University of Science and Technology Hanoi 100000 Viet Nam National Hospital of Tropical Diseases Hanoi Viet Nam Hanoi Medical University Hanoi Vietnam Hanoi Viet Nam Graduate School of Informatics and Engineering The University of Electro-Communications Tokyo 182-8585 Japan Center for Neuroscience and Biomedical Engineering The University of Electro-Communications Tokyo 182-8585 Japan

Objectives: In this study, an infection screening system was developed to detect patients suffering from infectious diseases. In addition, the system was also designed to deal with the variability in age and gender, which would affect the accuracy of the detection. Furthermore, to enable a low-cost, non-contact and embedded system, multiple vital signs from a medical radar were measured and all algorithms were implemented on a field programmable gate array, named PYNQ-Z1. Methods: The system consisted of two main stages: digital signal processing and data classification. In the former stage, Butterworth filters, with flexible cut-off frequencies depending on age and gender, and a time-domain peak detection algorithm were deployed to compute three vital signs, namely heart rate, respiratory rate, and standard deviation of heart beat-to-beat interval. For the classification problem, two machine learning models, Support Vector Machine and Quadratic Discriminant Analysis, were implemented. Results: The Student's t-test showed that our proposed digital signal processing algorithms coped well with the variability of human cases in age and gender. Meanwhile, the f₁-score of roughly 98.0% represented the high sensitivity and specificity of our proposed machine learning methods. Conclusion: This study outlines the implementation of an infection screening system, which achieved competent performance. The system might be beneficial for fast screening of infected patients at public health centers in underdeveloped areas, where people have little access to healthcare. © 2019

关键词： Digital signal processing Embedded system field programmable gate array Infection screening Machine learning

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：