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A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2017年第2期64卷 136-140页

作者： Abassi, Oussama Conde-Canencia, Laura Al Ghouwayel, Ali Boutillon, Emmanuel Univ Bretagne Sud Unite Mixte Rech UMR 6285 CNRS Lab STICC Lab F-56321 Lorient France Lebanese Int Univ Dept Comp & Commun Engn Beirut 146404 Lebanon

This brief presents an efficient architecture design for elementary-check-node processing in nonbinary low-density parity-check decoders based on the extended min-sum algorithm. This architecture relies on a simplified version of the bubble check algorithm and is implemented by the means of first-in-first-out. The adoption of this new design at the check node level results in a high-rate low-cost full-pipelined processor. A proof-of-concept implementation of this processor shows that the proposed architecture halves the occupied the field-programmable gate array (FPGA) surface and doubles the maximum frequency without modifying the input/output behavior of the previous one.

关键词： Channel coding communication systems decoding field programmable gate array

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The dynamical analysis of modified two-compartment neuron model and FPGA implementation

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PHYSICA A-STATISTICAL MECHANICS AND ITS APPLICATIONS 2017年 484卷 199-214页

作者： Lin, Qianjin Wang, Jiang Yang, Shuangming Yi, Guosheng Deng, Bin Wei, Xile Yu, Haitao Tianjin Univ Sch Elect Automat & Informat Engn Tianjin 300072 Peoples R China

The complexity of neural models is increasing with the investigation of larger biological neural network, more various ionic channels and more detailed morphologies, and the implementation of biological neural network is a task with huge computational complexity and power consumption. This paper presents an efficient digital design using piecewise linearization on field programmable gate array (FPGA), to succinctly implement the reduced two-compartment model which retains essential features of more complicated models. The design proposes an approximate neuron model which is composed of a set of piecewise linear equations, and it can reproduce different dynamical behaviors to depict the mechanisms of a single neuron model. The consistency of hardware implementation is verified in terms of dynamical behaviors and bifurcation analysis, and the simulation results including varied ion channel characteristics coincide with the biological neuron model with a high accuracy. Hardware synthesis on FPGA demonstrates that the proposed model has reliable performance and lower hardware resource compared with the original two-compartment model. These investigations are conducive to scalability of biological neural network in reconfigurable large-scale neuromorphic system. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Neuronal two-compartment model field programmable gate array Piecewise linearization Implementation

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Design and FPGA implementation of multiplierless comb filter

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2017年第11期45卷 1497-1513页

作者： Barsainya, Richa Agarwal, Meenakshi Rawat, Tarun Kumar Netaji Subhas Inst Technol Div ECE Room 135Sect 3 Dwarka New Delhi India

The main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements;therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first-order and second-order all-pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round-off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan-6 and Virtex-6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright (c) 2017 John Wiley & Sons, Ltd.

关键词： digital signal processing comb filter field programmable gate array Lattice wave digital filter canonic signed digit code

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Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing

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IET CIRCUITS DEVICES & SYSTEMS 2017年第3期11卷 274-279页

作者： Krishna, Mohan Krishna Gopi Roohi, Arman Zand, Ramtin DeMara, Ronald F. Univ Cent Florida Dept Elect & Comp Engn Comp Architecture Lab Orlando FL 32816 USA

field programmable gate array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realised by leveraging the complementary benefits of emerging devices with complementary metal oxide semiconductor (CMOS)-based devices. A novel carbon/magnet lookup table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous technologies to balance energy, delay, and reliability attributes. Herein, magnetic spintronic devices are employed in the configuration memory to contribute non-volatility and high scalability. Meanwhile, carbon nanotube field-effect transistors (CNFETs) provide desirable conductivity, low delay, and low power consumption. The proposed CM-LUT offers ultra-low power and high-speed operation while maintaining high endurance re-programmability with increased radiation-induced soft-error immunity. The proposed four-input one-output CM-LUT utilises 41 CNFETs and 20 magnetic tunnel junctions for read operations and 35 CNFET to perform write operations. Results indicate that CM-LUT achieves an average four-fold energy reduction, eight-fold faster circuit operation and 9.3% reconfiguration power delay product improvement in comparison with spin-based look-up tables. Finally, additional hybrid technology designs are considered to balance performance with the demands of energy consumption for near-threshold operation.

关键词： carbon nanotube field effect transistors field programmable gate arrays CMOS integrated circuits table lookup magnetoelectronics low-power electronics radiation hardening (electronics) magnetic tunnelling heterogeneous energy-sparing reconfigurable logic spin-based storage CNFET-based multiplexing field programmable gate array FPGA logic configurability bitstream storage dynamic signal routing complementary metal oxide semiconductor CMOS-based devices carbon magnet lookup table CM-LUT mixed heterogeneous technologies magnetic spintronic devices configuration memory carbon nanotube field-effect transistors low power consumption high-speed operation high endurance re-programmability radiation-induced soft-error immunity magnetic tunnel junctions four-fold energy reduction eight-fold faster circuit operation reconfiguration power delay product improvement

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FPGA-Based Implementation of Size-Adaptive Privacy Amplification in Quantum Key Distribution

IEEE PHOTONICS JOURNAL

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IEEE PHOTONICS JOURNAL 2017年第6期9卷 1-8页

作者： Yang, Shen-Shen Bai, Zeng-Liang Wang, Xu-Yang Li, Yong-Min Shanxi Univ State Key Lab Quantum Opt & Quantum Opt Devices Collaborat Innovat Ctr Extreme Opt Inst Optoelect Taiyuan 030006 Shanxi Peoples R China

In a quantum key distribution (QKD) system, privacy amplification (PA) is an essential procedure that can effectively eliminate the leaked information to an eavesdropper and distill a secret key. The processing speed of the PA algorithm inevitably affects the final key rate of the QKD system. We propose a high-speed PA algorithm based on field-programmable gate array (FPGA), where the matrix multiplications are divided into a number of rhomboid-block operations. The implementation of the PA reduces significantly the required number of FPGA Block RAMs. Meanwhile, it automatically adapts to different lengths of input and output blocks. Finally, we verified the correctness and high-speed of the algorithm when implemented in a Xilinx Virtex-7 FPGA.

关键词： Quantum key distribution privacy amplification hardware implementation field programmable gate array size-adaptive

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FDST-based PQ event detection and energy metering implementation on FPGA-in-the-loop and NI-LabVIEW

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2017年第4期11卷 453-463页

作者： Jaiswal, Supriya Ballal, Makarand S. Visvesvaraya Natl Inst Technol Dept Elect Engn Nagpur 440010 Maharashtra India

Power quality (PQ) is crucial parameter in determining the robustness and accuracy of any energy-metering algorithm. It immensely affects the performance of energy meters in terms of measurement accuracy. This study presents digital implementation of fast discrete Stockwell transform (FDST) with automatic scaling for accurate PQ-event detection (ED) and energy metering. Comparative analysis of FDST-based energy-metering algorithm is carried out with existing algorithms such as fast Fourier transform and filter-based design. The results demonstrate that FDST-based energy-metering algorithm surpasses existing algorithms in terms of accuracy, complexity, and adaptability under PQ events. In addition, new statistical features are proposed to classify and measure PQ events. The real-time implementation of the proposed FDST-based smart energy meter (SEM) is performed in national instruments (NI) laboratory virtual instrument engineering workbench (LabVIEW) and validated through field programmable gate array (FPGA)-in-the-loop using MATLAB and Altera Cyclone IV E FPGA board. The experimental results show satisfactory performance in terms of accuracy and resource utilisation. The effect of PQ events over energy metering is evaluated in terms of percentage loss in billing units. The features of the proposed SEM virtual instrument are real-time accurate PQ-ED, energy metering, loss evaluation, data logging, and remote control access.

关键词： fast Fourier transforms smart meters power meters field programmable gate arrays mathematics computing virtual instrumentation data loggers fast discrete Stockwell transform power quality-event detection energy-metering algorithm fast Fourier transform filter-based design smart energy meter NI-LabVIEW field programmable gate array MATLAB ALTERA Cyclone IV E FPGA board SEM virtual instrument loss evaluation data logging remote control access

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FPGA-based ultrasonic energy mapping with source removal method for damage visualization in composite structures

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ADVANCED COMPOSITE MATERIALS 2017年第Sup1期26卷 3-13页

作者： Abbas, Syed Haider Thanh Chung Truong Lee, Jung-Ryul Korea Adv Inst Sci & Technol Dept Aerosp Engn Daejeon South Korea

This paper presents the implementation of an ultrasonic energy mapping (UEM) method in a field programmable gate array (FPGA)-based processing board. This method is integrated into an ultrasonic propagation imaging (UPI) system for real-field application. UEM method involves two-dimensional Fourier transform and wavenumber filtering to capture the energy scattering waves. Performing multi-dimensional Fourier transform in FPGA is a challenging task because it cannot fit into a single FPGA chip, and therefore, external memory is required to handle a large amount of data. The row-column decomposition method is used to perform 2D Fourier transform using two DDR3 SDRAM memories. Additionally, a source removal function is added into the system to highlight the damage when high energy at the source location occurs. The UPI system was applied for inspection of a composite wing box with impact damages. The UEM results showed that a damage of 20x20mm(2) was detected successfully in the presence of the source inside the scan area. Moreover, the UEM result is produced in less than 5 s for 57,600 points, which is practical for a real-world, non-destructive testing application.

关键词： non-destructive testing ultrasonic propagation imager ultrasonic energy mapping composite structures field programmable gate array

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Reduced switch count pulse width modulated multilevel inverter

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IET POWER ELECTRONICS 2017年第1期10卷 10-17页

作者： Jayabalan, Maalmarugan Jeevarathinam, Baskaran Sandirasegarane, Thamizharasan Surya Grp Inst Dept Elect & Elect Engn GST Rd Villupuram India Adhiparasakthi Engn Coll Dept Elect & Elect Engn Melmaruvathur India

The study develops a new topology for a single phase cascaded H-bridge multilevel inverter (CHBMLI) with a focus to reduce the number of power switching devices in the path for the flow of current. The philosophy combines an array of series connected voltage sources on either side of an H-bridge inverter to derive the new configuration for the MLI. It allows a multicarrier pulse width modulation approach to the process of generating the pulses for synthesising the PWM output voltage. The use of a smaller number of switches to reach the output voltage show cases the ability of the modular architecture to expand the scope of the CHBMLI. The architecture of a field programmable gate array fosters to realise its implementation and validate the simulated results over a range of modulation indices. The performance draws a new directive in the choice of a particular topology for the MLI to suit applications in the real world.

关键词： PWM invertors field programmable gate arrays switches reduced switch count pulse width modulated multilevel inverter single phase cascaded H-bridge multilevel inverter CHBMLI power switching devices reduction current flow series connected voltage sources multicarrier pulse width modulation approach PWM output voltage modular architecture field programmable gate array modulation indices

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FPGA Controlled Five- Level Soft Switching Full Bridge DC-DC Converter Topology

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JOURNAL OF ELECTRICAL SYSTEMS 2017年第2期13卷 266-284页

作者： Prasad, J. Sivavara Obulesh, Y. P. Babu, Ch. Sai LBRCE Dept EEE Mylavaram 521230 India KL Univ Dept EEE Vaddeswaram India JNTUK Kakinda Dept EEE Kakinada India

The use of conventional dc-dc converter is likely to decrease the efficiency because of the hard switching, which generates switching losses during switching on/off states. The proposed converter has the following desirable features: It requires only five control switches out of which four main control switches operate under zero voltage switching and one auxiliary control switch which operates under zero current switching;Three level voltage waveform before output filter can be achieved, which significantly reduces the value of filter inductance as compared to the existing topologies;Soft switching occurs at small value of leakage inductance of high frequency transformer;Modified phase shift pulse width modulated control method is used to achieve wide output range. Hence, the cost and switching losses are reduced to a greater extent, thus improves the overall efficiency of a system. This paper describes the main operational modes and design equations of the proposed converter. The simulation and experimental results are presented to validate the feasibility of proposed work.

关键词： Soft switching Zero current switching (ZCS) Zero voltage switching (ZVS) Modified Phase Shift Pulse Width Modulation field programmable gate array

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Picosecond precision time-of-flight digital converter

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ELECTRONICS LETTERS 2017年第5期53卷 304-305页

作者： Wieczorek, G. Oliwa, W. Silesian Tech Univ Inst Elect Fac Automat Control Elect & Comp Sci Gliwice Poland

Time-of-flight (TOF) digital converter implemented in field programmable gate array has been introduced. The operation is based on train of pulses transmission and counting received pulses in bank of counters. The bank of counters clock signal and the transmitted pulses clock signal are slightly different in frequency. This small difference is a key factor for the measurement method and is achieved by phase locked loop. TOF for the transmitted pulses is directly calculated upon counters counts. Time interval resolution for the prototype instrument is 10.4 ps and average RMS uncertainty value is 12.3 ps. There is no need for special calibration. TOF digital converter requires minimum amount of resources and is suitable for low-cost applications.

关键词： field programmable gate arrays clocks phase locked loops picosecond precision time-of-flight digital converter TOF digital converter field programmable gate array pulse transmission bank of counter clock signal transmitted pulses clock signal measurement method phase locked loop time 10 4 ps time 12 3 ps

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