检索结果-内蒙古大学图书馆

A High-Linearity, Ring-Oscillator-Based, Vernier Time-to-Digital Converter Utilizing Carry Chains in FPGAs

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2017年第1期64卷 697-704页

作者： Cui, Ke Ren, Zhongjie Li, Xiangyu Liu, Zongkai Zhu, Rihong Nanjing Univ Sci & Technol MIIT Key Lab Adv Solid Laser Nanjing Jiangsu Peoples R China Nanjing Univ Sci & Technol Adv Launching Coinnovat Ctr Nanjing Jiangsu Peoples R China Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing Jiangsu Peoples R China

Time-to-digital converters (TDCs) using dedicated carry chains of field programmable gate arrays (FPGAs) are usually organized in tapped-delay-line type which are intensively researched in recent years. However this method incurs poor differential nonlinearity (DNL) which arises from the inherent uneven bin granularity. This paper proposes a TDC architecture which utilizes the carry chains in a quite different manner in order to alleviate this long-standing problem. Two independent carry chains working as the delay lines for the fine time interpolation are organized in a ring-oscillator-based Vernier style and the time difference between them is finely adjusted by assigning different number of basic delay cells. A specific design flow is described to obtain the desired delay difference. The TDC was implemented on a Stratix III FPGA. Test results show that the obtained resolution is 31 ps and the DNL\ INL is in the range of (-0.080 LSB, 0.073 LSB)\(-0.087 LSB, 0.091 LSB). This demonstrates that the proposed architecture greatly improves linearity compared to previous techniques. Additionally the resource cost is rather low which uses only 319 LUTs and 104 registers per TDC channel.

关键词： Carry chain field programmable gate array high linearity ring oscillator time-to-digital converter Vernier delay line

来源：评论

学校读者我要写书评

暂无评论

Area-Efficient LUT-Like programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm

引用

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2017年第7期E100A卷 1418-1426页

作者： Higashi, Toshiki Ochi, Hiroyuki Ritsumeikan Univ Grad Sch Informat Sci & Engn Kusatsu 5258577 Japan Ritsumeikan Univ Dept Comp Sci Coll Informat Sci & Engn Kusatsu 5258577 Japan

This paper proposes 0-1-A-A LUT, a new programmable logic using atom switches, and a delay-optimal mapping algorithm for it. Atom switch is a non-volatile memory device of very small geometry which is fabricated between metal layers of a VLSI, and it can be used as a switch device of very small on-resistance and parasitic capacitance. While considerable area reduction of Look Up Tables (LUTs) used in conventional field programmable gate arrays (FPGAs) has been achieved by simply replacing each SRAM element with a memory element using a pair of atom switches, our 0-1-A-A LUT achieves further area and delay reduction. Unlike the conventional atom-switch-based LUT in which all k input signals are fed to a MUX, one of input signals is fed to the switch array, resulting area reduction due to the reduced number of inputs of the MUX from 2k to 2k-1, as well as delay reduction due to reduced fanout load of the input buffers. Since the fanout of this input buffers depends on the mapped logic function, this paper also proposes technology mapping algorithms to select logic function of fewer number of fanouts of input buffers to achieve further delay reduction. From our experiments, the circuit delay using our k-LUT is 0.94% smaller in the best case compared with using the conventional atom-switch-based k-LUT.

关键词： field programmable gate array look-up table non-volatile resistive-change element technology mapping for combinational circuit

来源：评论

学校读者我要写书评

暂无评论

Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

引用

MULTIMEDIA TOOLS AND APPLICATIONS 2017年第11期76卷 13197-13219页

作者： Shet, K. Sathish Aswath, A. R. Hanumantharaju, M. C. Gao, Xiao-Zhi JSS Acad Tech Educ Dept Elect & Commun Engn Bengaluru India Dayananda Sagar Coll Engn Dept Telecommun Engn Bengaluru India BMS Inst Technol & Management Dept Elect & Commun Engn Bengaluru India Aalto Univ Sch Elect Engn Dept Elect Engn & Automat Espoo Finland

The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high-speed reconfigurable architectures have been designed for Least Significant Bit (LSB) or multi-bit based image steganography algorithm that suits field programmable gate arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) implementation. The architectures are designed and instantiated to implement the complete steganography system. The proposed system is competent enough to provide larger throughput, since high degrees of pipelining and parallel operations are incorporated at the module level. The evolved architectures are realized in Xilinx Virtex-II Pro XC2V500FG256-6 FPGA device using Register Transfer Level (RTL) compliant Verilog coding and has the capacity to work in real-time at the rate of 183.48 frames/second. Prior to the FPGA/ASIC implementation, the proposed steganography system is simulated in software to validate the concepts intended to implement. The hardware implemented algorithm is tested by varying embedding bit size as well as the resolution of a cover image. As it is clear from the results presented that the projected framework is superior in speed, area and power consumption compared to other researcher's method.

关键词： Image steganography Least Significant Bit Hiding/extraction Reconfigurable architectures Verilog field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Particle MCMC algorithms and architectures for accelerating inference in state-space models

引用

INTERNATIONAL JOURNAL OF APPROXIMATE REASONING 2017年 83卷 413-433页

作者： Mingas, Grigorios Bottolo, Leonardo Bouganis, Christos-Savvas Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England Univ Cambridge Dept Med Genet Cambridge CB2 OQQ England

Particle Markov Chain Monte Carlo (pMCMC) is a stochastic algorithm designed to generate samples from a probability distribution, when the density of the distribution does not admit a closed form expression. pMCMC is most commonly used to sample from the Bayesian posterior distribution in State-Space Models (SSMs), a class of probabilistic models used in numerous scientific applications. Nevertheless, this task is prohibitive when dealing with complex SSMs with massive data, due to the high computational cost of pMCMC and its poor performance when the posterior exhibits multi -modality. This paper aims to address both issues by: 1) Proposing a novel pMCMC algorithm (denoted ppMCMC), which uses multiple Markov chains (instead of the one used by pMCMC) to improve sampling efficiency for multi-modal posteriors, 2) Introducing custom, parallel hardware architectures, which are tailored for pMCMC and ppMCMC. The architectures are implemented on field programmable gate arrays (FPGAs), a type of hardware accelerator with massive parallelization capabilities. The new algorithm and the two FPGA architectures are evaluated using a large-scale case study from genetics. Results indicate that ppMCMC achieves 1.96x higher sampling efficiency than pMCMC when using sequential CPU implementations. The FPGA architecture of pMCMC is 12.1x and 10.1x faster than state-of-the-art, parallel CPU and GPU implementations of pMCMC and up to 53x more energy efficient;the FPGA architecture of ppMCMC increases these speedups to 34.9x and 41.8x respectively and is 173x more power efficient, bringing previously intractable SSM-based data analyses within reach. (C) 2016 The Authors. Published by Elsevier Inc.

关键词： Markov Chain Monte Carlo Particle filter field programmable gate array Bayesian inference Hardware acceleration

来源：评论

学校读者我要写书评

暂无评论

Reduced switch count pulse width modulated multilevel inverter

引用

IET POWER ELECTRONICS 2017年第1期10卷 10-17页

作者： Jayabalan, Maalmarugan Jeevarathinam, Baskaran Sandirasegarane, Thamizharasan Surya Grp Inst Dept Elect & Elect Engn GST Rd Villupuram India Adhiparasakthi Engn Coll Dept Elect & Elect Engn Melmaruvathur India

The study develops a new topology for a single phase cascaded H-bridge multilevel inverter (CHBMLI) with a focus to reduce the number of power switching devices in the path for the flow of current. The philosophy combines an array of series connected voltage sources on either side of an H-bridge inverter to derive the new configuration for the MLI. It allows a multicarrier pulse width modulation approach to the process of generating the pulses for synthesising the PWM output voltage. The use of a smaller number of switches to reach the output voltage show cases the ability of the modular architecture to expand the scope of the CHBMLI. The architecture of a field programmable gate array fosters to realise its implementation and validate the simulated results over a range of modulation indices. The performance draws a new directive in the choice of a particular topology for the MLI to suit applications in the real world.

关键词： PWM invertors field programmable gate arrays switches reduced switch count pulse width modulated multilevel inverter single phase cascaded H-bridge multilevel inverter CHBMLI power switching devices reduction current flow series connected voltage sources multicarrier pulse width modulation approach PWM output voltage modular architecture field programmable gate array modulation indices

来源：评论

学校读者我要写书评

暂无评论

A design method of digital deconvolution filter for on-line compensation of system dynamic characteristic

A design method of digital deconvolution filter for on-line ...

引用

IEEE International Instrumentation and Measurement Technology Conference (I2MTC) - Discovering New Horizons in Instrumentation and Measurement

作者： Zhao Chenyang Zhang Zhijie North Univ China Sch Instrument & Elect Taiyuan 030051 Shanxi Peoples R China North Univ China Key Lab Instrumentat Sci & Dynam Measurement Minist Educ Taiyuan 030051 Shanxi Peoples R China North Univ China Automat Test Equipment & Syst Engn Res Ctr Shanxi Taiyuan Shanxi Peoples R China

ISBN: (纸本)9781538622223

The traditional digital deconvolution filter which is influenced by its structure has some problems in online compensation of the test system, such as instability, slow speed, and low precision. So we design a digital BR deconvolution filter which can be realized on field programmable gate array to compensate the dynamic characteristics of the test system quickly and use the cascaded structures which is easy to realize zeros and poles to design 4-stage cascaded differential compensation module which is assigned for the zero-pole. The Xilinx Spartan 6 platform is used to verify the stability and real-time performance of the module whose parameters are quantified, through dynamic calibration experiment to analyze dynamic compensation effect of Endevco 8530c pressure sensor and its test system of dynamic compensation effect on the time and frequency domain characteristics. Compare the result of compensation by direct type I structure, this kind of digital filter design method has the advantages of small quantitative impact, fast calculation speed, and configurable parameters, to some extent make up for the defect of the online compensation system characteristics.

关键词： digital deconvolution filter dynamic compensation cascaded IIR pole-zero assignment field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

引用

MICROPROCESSORS AND MICROSYSTEMS 2017年 52卷 131-144页

作者： Johnson, Anju P. Patranabis, Sikhar Chakraborty, Rajat Subhra Mukhopadhyay, Debdeep Univ York Dept Elect Engn York YO10 5DD N Yorkshire England Indian Inst Technol Dept Comp Sci & Engn Kharagpur 721302 W Bengal India

The advent of the Internet of Things has motivated the use of field programmable gate array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities for dynamic non-invasive modifications to circuits implemented on the FPGA. In particular, the ability to perform DPR over the network is essential in the context of a growing number of Internet of Things (IoT)-based and embedded security applications. However, the use of remote DPR brings with it a number of security threats that could lead to potentially catastrophic consequences in practical scenarios. In this paper, we demonstrate four examples where the remote DPR capability of the FPGA may be exploited by an adversary to launch Hardware Trojan Horse (HTH) attacks on commonly used security applications. We substantiate the threat by demonstrating remotely-launched attacks on Xilinx FPGA-based hardware implementations of a cryptographic algorithm, a true random number generator, and two processor based security applications - namely, a software implementation of a cryptographic algorithm and a cash dispensing scheme. The attacks are launched by on-the-fly transfer of malicious FPGA configuration bitstreams over an Ethernet connection to perform DPR and leak sensitive information. Finally, we comment on plausible countermeasures to prevent such attacks. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Internet of things Dynamic Partial Reconfiguration field programmable gate array Hardware Trojan Horse Hardware security

来源：评论

学校读者我要写书评

暂无评论

Unified Communication Framework

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2017年第10期64卷 2761-2764页

作者： Gaisbauer, Dominic Bai, Yunpeng Huber, Stefan Konorov, Igor Levit, Dymitro Paul, Stephan Steffen, Dominik Tech Univ Munich Inst Hadron Struct & Fundamental Symmetries D-85748 Garching Germany

The unified communication framework (UCF) is a unified network protocol and field programmable gate array core for high-speed serial interfaces employed in data acquisition systems. It provides up to 64 different communication channels via a single serial link. One channel is reserved for timing and trigger information, whereas the other channels can be used for slow control interfaces and data transmission. All channels except the timing are bidirectional and share network bandwidth according to assigned priority. The timing channel distributes messages with fixed and deterministic latency in one direction. In this regard, the protocol implementation is asymmetric. The precision of the timing channel is given by the jitter of the recovered clock and is typically in the order of 10-20 ps rms. The timing channel has highest priority and a slow control interface should use the second highest priority channel in order to avoid long delays due to high traffic on other channels. The framework supports point-to-point connections and starlike 1:n topologies for optical networks with a passive splitter. It always employs one of the connection parties as a master and the others as slaves. The starlike topology can be used for front ends with low data rates or pure time distribution systems. In this case, the master broadcasts information according to assigned priority, whereas the slaves communicate in a time sharing manner to the master. In the open systems interconnection layer model, the UCF can be classified as layers one to three, which includes the physical, the data, and the network layer.

关键词： Data Acquisition fixed latency transmission field programmable gate array optical transmitters slow control transport protocols

来源：评论

学校读者我要写书评

暂无评论

Exploring Two-Dimensional Magnetic Recording Gain Constraints

引用

IEEE TRANSACTIONS ON MAGNETICS 2017年第2期53卷 1-4页

作者： Alexander, James Ngo, Tue Dahandeh, Shafa Western Digital Irvine CA 92612 USA Western Digital San Jose CA 95138 USA

Two-dimensional magnetic recording (TDMR) offers the opportunity to provide areal density (AD) gain, but questions were unanswered as to how the gain is achieved and what can be done to maximize the gain from this new technology. In this paper, we offer some reasons why different investigators might report different AD gain opportunities. We present data collected on a spin stand with two reader heads and processed with a commercially available field programmable gate array TDMR channel. The implications of this paper should provide guidelines on reader geometries, placement, and performance.

关键词： Bit-patterned media recording conventional magnetic recording (CMR) field programmable gate array heat-assisted magnetic recording shingled magnetic recording TDMR

来源：评论

学校读者我要写书评

暂无评论

Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices

引用

INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2017年第4期9卷 337-352页

作者： Barbareschi, Mario Bagnasco, Pierpaolo Univ Naples Federico II Dept Elect Engn & Informat Technol Naples NA Italy

field programmable gate array (FPGA) technology is being adopted in many digital systems, hence the demand for security increases, especially when intrinsic vulnerabilities of programmable devices jeopardise the intellectual properties (IPs). New high and medium-end FPGA devices have built-in mechanisms that, exploiting encryption primitives, are able to avoid IP piracy by preventing cloning and reverse engineering, but low-end FPGA families still lack security solutions. Recently, in the literature, a great researching effort has been done on physically unclonable functions (PUFs), which are eligible to be a fundamental means for authenticating integrated circuits. They can be adopted to guarantee protection against IP violations by implementing locking finite state machines (FSMs) on any device. In this paper, we show two implementations of the Anderson PUF, a good scalable and high reliable PUF architecture, on the Xilinx Spartan-3E family, which can be adopted to introduce the locking mechanism. In the experimental result, we show the quality parameters for signatures generated from proposed Anderson PUFs and the overhead introduced by the locking mechanism through an FSM.

关键词： IP protection field programmable gate array FPGA security physically unclonable functions PUFs fuzzy extractor Anderson PUF Xilinx Spartan-3E

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：