检索结果-内蒙古大学图书馆

IEEE International Conference on Control Applications Part of 2010 IEEE Multi-Conference on Systems and Control

作者： Sun, Yifan Fang, Yongchun Zhang, Yudong Dong, Xiaokun Nankai Univ Inst Robot & Automat Informat Syst IRAIS Tianjin 300071 Peoples R China

ISBN: (纸本)9781424453634

This report describes the realization of an embedded hardware system designed to perform fast control for an atomic force microscope (AFM). Traditional implementation of control algorithms for AFMs, either PC-based or DSP-based, does not meet the high-speed scanning requirement. Considering the capability of parallel computing, FPGA is employed to achieve real-time control for an AFM equipment. Specifically, in the designed embedded system, the hardware includes several key components of signal acquisition, signal conversion, data communication as well as the FPGA-based control law implementation. Besides higher control frequency, the designed FPGA-based embedded system provides a general platform for different advanced control strategies, on which a variety of control algorithms can be implemented and tested conveniently by replacing the codes in the software rather than changing hardware structure, due to the merit that FPGA can integrate internal CPU and it has a large number of logic cells and soft-cores. The widely utilized proportional-integral-derivative (PID) algorithm is chosen as an example to demonstrate the implementation of a controller by using powerful hardware description tools.

关键词： AFM real-time control FPGA-based control law atomic force microscope atomic force microscopy embedded hardware system design embedded systems field programmable gate array field programmable gate arrays parallel computing proportional-integral- derivative algorithm three-term control

来源：评论

学校读者我要写书评

暂无评论

Design and Realization of ADC based on FPGA

Design and Realization of ADC based on FPGA

引用

2018 联合国际先进工程与技术研究国际会议

作者： Jing Wu School of Intelligence Science and Information Engineering Xi'an Peihua University

In this paper, the signal collected by WM8731 that is a high resolution analog to digital controller(ADC) is set to establish custom NIOS II central processing unit(CPU) and peripheral controlling in the system on a programmable chip(SOPC) Builder, systems developing tool, of Altera Quartus II that is a developing software. The design and realization of ADC based on FPGA is designed, ran, compiled and simulated in Quartus II. The Design and Realization of ADC Based on field programmable gate array(FPGA) combines the advantages of embedded system and FPGA and provides a new design method of digital signal processing system of high performance. The improved method is proved to be effective.

关键词： Analog to digital controller Central processing unit field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Presilicon evaluation on Correlation Power Analysis attacks and countermeasures 23

Presilicon evaluation on Correlation Power Analysis attacks ...

引用

23rd IEEE International Symposium for Design and Technology in Electronic Packaging (SIITME)

作者： Damian, B. M. Hascsi, Z. Sandulescu, A. B. Univ Politehn Bucuresti Dept Elect Devices Circuits & Architectures Bucharest Romania Chip Card & Secur Infineon Bucharest Romania

ISBN: (纸本)9781538616260

Side channel attacks can retrieve sensitive information from secured chips without any invasive procedures. Such a powerful attack is the Correlation Power Analysis (CPA), which makes use of the power traces to gain information regarding the processed data. This paper investigates its efficiency, having different FPGAs under test. The main characteristics of a suitable test environment are highlighted. Additionally, this paper proposes a countermeasure against this type of attack.

关键词： Side Channel Attack Correlation Power Analisys field programmable gate array Countermeasures

来源：评论

学校读者我要写书评

暂无评论

Parallel implementation of aircraft disembarking and emergency evacuation based on cellular automata

引用

INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2017年第2期31卷 134-151页

作者： Giitsidis, Themistoklis Dourvas, Nikolaos I. Sirakoulis, Georgios Ch Democritus Univ Thrace Dept Elect & Comp Engn GR-67100 Xanthi Greece

In this paper we present a model based on the parallel computational tool of cellular automata (CA) capable of simulating the process of disembarking in a small airplane seat layout, corresponding to Airbus A320/ Boeing 737 layout, in search of ways to make it faster and safer under normal evacuation conditions, as well as emergency scenarios. The proposed model is highly customizable, with the number of exits, the walking speed of passengers, depending on their sex, age and height, and the effects of retrieving and carrying luggage. Additionally, the presence of obstacles in the aisles as well as the emergence of panic being parameters whose values can be varied in order to enlighten the disembarking and emergency evacuation processes are considered in detail. The simulation results were compared to existing aircraft disembarking and evacuation times and indicate the efficacy of the proposed model in investigating and revealing passenger attributes during these processes in all the examined cases. Moreover, we parallelized our code in order to run on a graphics processing unit (GPU) using the CUDA programming language, speeding up the simulation process. Finally, in order to present a fully dynamical anticipative real-time system helpful for decision-making we implemented the proposed CA model in a field programmable gate array (FPGA) device, and recreated the results given by the software simulations in a fraction of the time. We then compared and exported the performance results among a sequential software implementation, the implementation running on a GPU, and a hardware implementation, proving the consequent acceleration that results from the parallel CA implementation in specific hardware.

关键词： Cellular automata aircraft disembarking emergency evacuation modelling crowd dynamics graphics processing unit hardware field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Design of multifunctional signal source based on FPGA 3rd

Design of multifunctional signal source based on FPGA

引用

3rd International Conference of Electronic Engineering and Information Science (ICEEIS)

作者： Wang, P. Liang, C. Shao, M. L. Han, X. Harbin Univ Sci & Technol Sch Elect & Elect Engn Harbin Heilongjiang Peoples R China

ISBN: (纸本)9781315265278;9781138029873

Direct Digital frequency Synthesis (DDS) has the characteristics of fast frequency conversion speed, high frequency stability, and low phase noise. In this paper, the field programmable gate array (FPGA) was chosen as the core chip to realize the design of the multifunctional signal source based on DDS technology. The signal source can generate five kinds of waveforms. They are respectively sine wave, square wave, triangle wave, increased saw tooth wave and decreased saw tooth wave. The frequency range of the output signals is 0 Hz similar to 1 MHz, and the amplitude range is 0 V similar to 12 V. The simulation and experimental results show that the signal source has such advantages as multifunctional waveform signal, stable waveform signal, low cost and programmability.

关键词： direct digital frequency synthesis multifunctional signal source field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Designing low complexity computational intelligence modules in FPGA using high level synthesis tools 5

Designing low complexity computational intelligence modules ...

引用

5th International Symposium on Electrical and Electronics Engineering (ISEEE)

作者： Dogaru, Ioana Dogaru, Radu Univ Politehn Bucuresti Dept Appl Elect & Informat Engn Nat Comp Lab Bucharest Romania

ISBN: (纸本)9781538620595

High level synthesis tools offered by either FPGA (field programmable gate array) vendors or from the public domain are evaluated in order to generate efficient and low complexity computational intelligence modules. This paper reports specific issues and comparative synthesis results in implementing basic modules of the FSVC classifier (Fast Support Vector Classifier) and cellular automata starting from an algorithmic description in high level languages such as Python and C/C++. Two particular HLS tools were considered, namely VivadoHLS from Xilinx and MyHDL.

关键词： High-level synthesis field programmable gate array Hardware Description Languages cellular automata

来源：评论

学校读者我要写书评

暂无评论

A Novel Current Estimation Technique for Digital Controlled Switching Converters Operating in CCM and DCM 9

A Novel Current Estimation Technique for Digital Controlled ...

引用

9th Annual IEEE Energy Conversion Congress and Exposition (ECCE)

作者： Channappanavar, Rajat Mishra, Santanu Indian Inst Technol Kanpur Dept Elect Engn Kanpur Uttar Pradesh India

ISBN: (纸本)9781509029983

Inductor current in the high speed switching converters is used as a feedback signal for current mode control and over current fault protection. Sensing inductor current for the use of digital controllers require high bandwidth current sensors and also need high speed Analog to Digital Converter (ADC) to convert the sensed current into digital domain. Use of high bandwidth current sensors and high speed ADCs make the sensing costly and complimented. Hence, eliminating current sensor and ADCs is in the interest of the present day research. These can be eliminated by estimating inductor current instead of sensing it. The estimation process uses converter voltages easily sensed using slow ADCs. This paper proposes a novel high bandwidth digital inductor current estimation technique which using low cost comparators. This technique estimates both DC and switching frequency components of the inductor current. The estimation is accurate to 9 % of the actual current irrespective of the converter operating in Continuous or Discontinuous Conduction Mode (CCM/DCM). The theory and its practical implementation procedures are given in detail. The proposed theory is validated with the experimental results on a 98 kHz, 3.3 V / 10 A buck converter working in CCM and DCM.

关键词： Continuous Conduction Mode Discontinuous Conduction Mode Analog to Digital Converter Digital to Analog Converter Current Sensor Digital Control field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation 24th

A Hardware-Oriented Dropout Algorithm for Efficient FPGA Imp...

引用

24th International Conference on Neural Information Processing (ICONIP)

作者： Yeoh, Yoeng Jye Morie, Takashi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan

ISBN: (纸本)9783319701363;9783319701356

This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

关键词： Neural networks Dropout field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Performance Comparison of the Improved Power-Throughput AES and Blowfish Algorithms on FPGA 9th

引用

9th International Conference on Robotic, Vision, Signal Processing and Power Applications (RoViSP)

作者： Ahmad, R. Ismail, W. Sains USM Collaborat Microelect Design Excellence Ctr CEDEC Level 1Block C10 Persiaran Bukit Jambul George Town 11900 Malaysia Sch Elect & Elect Engn Auto ID Lab Engn Campus Nibong Tebal 14300 Penang Malaysia

ISBN: (纸本)9789811017216;9789811017193

The demand for wireless broadband access through mobile devices has increased impressively causing wireless security to be a very serious concern. Most of wireless communication standards implement an advanced encryption standard (AES) algorithm for protection against various classes of wireless attack such as interception, fabrication, modification and reply attacks. However, the AES is a complex algorithm that consumes more memory, time, and battery power. In this paper, the performance of the proposed AES and Blowfish algorithms with improved power-throughput are analysed and compared using Virtex6 field programmable gate array (FPGA) in terms of their architecture, throughput and power consumption. The results show that the proposed Blowfish has reduced slices usage and power consumption by 1 and 6 % respectively, and increased the throughput by 36 %.

关键词： Security Advanced encryption standard Blowfish field programmable gate array Throughput Power consumption

来源：评论

学校读者我要写书评

暂无评论

Hardware Accelerator for Skin Color Detection Technique

Hardware Accelerator for Skin Color Detection Technique

引用

International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)

作者： Sharma, Megha Verma, Seema Banasthali Univ Dept Elect Vanasthali Rajasthan India

ISBN: (纸本)9781509032433

A very important research area for automated video surveillance systems is skin color detection. Major issues for these systems are real time requirements. In this paper, a block based skin color detection technique is proposed. Results prove that it is a robust and efficient technique. Skin color regions in an image can be detected with the proposed technique. A performance gain of 3.58 times is achieved in results. The algorithms is implemented in C language on a WindowXP machine usind Dev-C++ compiler (Version 4.9.9.2). The experimental results have established the effectiveness and accuracy of the approach. The proposed algorithm is then implemented on Virtex-4 FPGA platform.

关键词： Skin Color Detection YCrCb Color Space field programmable gate array Hardware Accelerator

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：