作者：
Ahmad, R.Ismail, W.Sains USM
Collaborat Microelect Design Excellence Ctr CEDEC Level 1Block C10 Persiaran Bukit Jambul George Town 11900 Malaysia Sch Elect & Elect Engn
Auto ID Lab Engn Campus Nibong Tebal 14300 Penang Malaysia
The demand for wireless broadband access through mobile devices has increased impressively causing wireless security to be a very serious concern. Most of wireless communication standards implement an advanced encrypt...
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ISBN:
(纸本)9789811017216;9789811017193
The demand for wireless broadband access through mobile devices has increased impressively causing wireless security to be a very serious concern. Most of wireless communication standards implement an advanced encryption standard (AES) algorithm for protection against various classes of wireless attack such as interception, fabrication, modification and reply attacks. However, the AES is a complex algorithm that consumes more memory, time, and battery power. In this paper, the performance of the proposed AES and Blowfish algorithms with improved power-throughput are analysed and compared using Virtex6 field programmable gate array (FPGA) in terms of their architecture, throughput and power consumption. The results show that the proposed Blowfish has reduced slices usage and power consumption by 1 and 6 % respectively, and increased the throughput by 36 %.
A very important research area for automated video surveillance systems is skin color detection. Major issues for these systems are real time requirements. In this paper, a block based skin color detection technique i...
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ISBN:
(纸本)9781509032433
A very important research area for automated video surveillance systems is skin color detection. Major issues for these systems are real time requirements. In this paper, a block based skin color detection technique is proposed. Results prove that it is a robust and efficient technique. Skin color regions in an image can be detected with the proposed technique. A performance gain of 3.58 times is achieved in results. The algorithms is implemented in C language on a WindowXP machine usind Dev-C++ compiler (Version 4.9.9.2). The experimental results have established the effectiveness and accuracy of the approach. The proposed algorithm is then implemented on Virtex-4 FPGA platform.
Inductor current in the high speed switching converters is used as a feedback signal for current mode control and over current fault protection. Sensing inductor current for the use of digital controllers require high...
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ISBN:
(纸本)9781509029983
Inductor current in the high speed switching converters is used as a feedback signal for current mode control and over current fault protection. Sensing inductor current for the use of digital controllers require high bandwidth current sensors and also need high speed Analog to Digital Converter (ADC) to convert the sensed current into digital domain. Use of high bandwidth current sensors and high speed ADCs make the sensing costly and complimented. Hence, eliminating current sensor and ADCs is in the interest of the present day research. These can be eliminated by estimating inductor current instead of sensing it. The estimation process uses converter voltages easily sensed using slow ADCs. This paper proposes a novel high bandwidth digital inductor current estimation technique which using low cost comparators. This technique estimates both DC and switching frequency components of the inductor current. The estimation is accurate to 9 % of the actual current irrespective of the converter operating in Continuous or Discontinuous Conduction Mode (CCM/DCM). The theory and its practical implementation procedures are given in detail. The proposed theory is validated with the experimental results on a 98 kHz, 3.3 V / 10 A buck converter working in CCM and DCM.
Lightweight block ciphers are an important topic of research in the context of the Internet of Things (IoT). Current cryptographic contests and standardization efforts seek to benchmark lightweight ciphers in both har...
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ISBN:
(纸本)9789090304281
Lightweight block ciphers are an important topic of research in the context of the Internet of Things (IoT). Current cryptographic contests and standardization efforts seek to benchmark lightweight ciphers in both hardware and software. Although there have been several benchmarking studies of both hardware and software implementations of lightweight ciphers, direct comparison of hardware and software implementations is difficult due to differences in metrics, measures of effectiveness, and implementation platforms. In this research, we facilitate this comparison by use of a custom lightweight reconfigurable processor. We implement six ciphers, AES, SIMON, SPECK, PRESENT, LED and TWINE, in hardware using register transfer level (RTL) design, and in software using the custom reconfigurable processor. Both hardware and software implementations are instantiated in identical Xilinx Kintex-7 FPGAs, which enables direct comparison of throughput, area, throughput-to-area (TP/A) ratio, power, and energy. Results show that TWINE and AES have the highest TP/A ratios for hardware and software implementations, respectively, assuming an area target of 300 - 450 LUTs. In terms of direct comparison, software implementations on tailored reconfigurable processers generally use less power - especially where reconfigurable instruction set extensions are permitted. However, custom hardware implementations have higher throughput and energy-efficiency than software implementations on the same platform.
Scan based error detection architectures for hybrid, carry-free radix-2 and radix-4 addition operations using redundant arithmetic are presented in this paper. Such addition operations have been chosen as representati...
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ISBN:
(纸本)9781538622933
Scan based error detection architectures for hybrid, carry-free radix-2 and radix-4 addition operations using redundant arithmetic are presented in this paper. Such addition operations have been chosen as representative examples as they are free from carry propagation delay and are ideal from the viewpoint of technology mapping of the logic elements onto the FPGA slices. The architectures have been conceived following the design paradigm of target FPGA specific primitive instantiation coupled with location constraints, without any degradation in the speed of circuit operation as compared to the original circuit implementation without the scan operation. Our architectures also comfortably outperform the existing state-of-the-art error detection architectures in terms of speed and consumes less area.
The employments of Multilevel DC Link Inverters offer dependable points of interest attributable to the expansion in the highest levels at the yield output voltage and are broadly acknowledged for industrial applicati...
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The employments of Multilevel DC Link Inverters offer dependable points of interest attributable to the expansion in the highest levels at the yield output voltage and are broadly acknowledged for industrial applications. The execution of these bores on high when contrasted with the routine conventional two-level inverters because of their drawbacks. Be that as it may, the expanded number of devices, complex PWM control, and voltage-adjusting issue are a portion of the hindrances. This paper goes for presenting another topology, which can perilously decrease the switch number by introducing a module called polarity generation module. This topology gives a DC voltage fit as a fiddle of a staircase which approximates the corrected state of a directed sinusoidal wave to the extension inverter, which thusly interchanges the extremity to deliver an AC voltage with low THD and switching loss. The topology is tested by adopting a choice of control techniques and enhanced execution of the proposed inverter contrasted with the overarching topologies. The FPGA has been selected to verify the proposed inverter with modulating technique due its advanced futures and computing facility. For validation, simulation and experimental results are offered. (C) 2017 The Authors. Published by Elsevier Ltd.
To improve the efficiency of bandwidth usage, the cognitive radios concept has emerged. Spectrum sensing is a pivotal function in cognitive radio systems so that the secondary users can be able to access the free spec...
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ISBN:
(纸本)9781538611913
To improve the efficiency of bandwidth usage, the cognitive radios concept has emerged. Spectrum sensing is a pivotal function in cognitive radio systems so that the secondary users can be able to access the free spectrum holes without interfering with primary users. Energy detection is the most common and easiest spectrum sensing technique for cognitive radios. In this paper, the conventional energy detection receiver operating characteristic curve and performance metrics are simulated under additive white Gaussian noise (AWGN) environment by using Monte Carlo simulation. Also, the performance of energy detection is analyzed under different types of M-ary modulation. The analysis of performance will carry the assumption of noise uncertainty. This performance gain is compared with conventional energy detection without any noise effect. In addition, the relation between a number of samples and signal to noise ratio wall (SNR wall) is provided and simulated. The simulation tool used in the analysis is MATLAB software. Finally, the implementation of energy detection technique in the time domain and frequency domain is designed on Xilinx Spartan-3E (XC3S500E-FG320) field programmable gate array (FPGA) kit by using Verilog language and Xilinx ISE Simulator version 14.1.
Due to increasing complexity of software in embedded systems, performance aspects become much more important this days. This should happen early in the development process. Often execution times and events are not eas...
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ISBN:
(纸本)9781538621462
Due to increasing complexity of software in embedded systems, performance aspects become much more important this days. This should happen early in the development process. Often execution times and events are not easily countable or measurable due to a lack of functionality in these systems. Execution time monitoring is also relevant in terms of reacting to internal and external events dynamically. Especially for systems using multiple tasks with internal or external resource dependencies, this is a major discipline. Another problem is that measurements during the development process are often done by interfering the system as a whole. This method leads to biases in the measurement results, because the finalized system gets deployed without these interfering functionalities and can therefore work more efficiently than the development system. The scope of the present work is to develop a module in a hardware description language (HDL) which is able to measure execution times and events task-aware and unaware without interfering the system. The measurements of this module must be handed to the programmer through an easy accessible interface. The main focuses of the project are the scalability, platform independency concerning processor and operating system (OS), as well as easy extendibility. Also, reusability of counters during runtime is included in this work.
This work proposed a sparse learning optimization based kidney image classification using Sparse Deep Neural Network (SDNN) similarity measure. The kidney images are acquired and preprocessed to improve the image qual...
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ISBN:
(纸本)9781509055555
This work proposed a sparse learning optimization based kidney image classification using Sparse Deep Neural Network (SDNN) similarity measure. The kidney images are acquired and preprocessed to improve the image quality. Then the method splits the image into number of sectional image which Crops the Image for Number of Times Using Feature Extraction Method. Feature extraction using Algebraic Histogram based Sum and difference model to extract the 2d and 3d features of kidney image. The textures features are segmented by Algebric histogram (AH) method and the features are optimized using the hardware model. Based on the sparse classification depthness measure the method identifies the region which has affected or abnormal. At the classification stage, the method computes the sparse learning based pixel similarity measure to identify the most affected region and to perform classification. The entire hardware model can be split into two important levels namely Algebric histogram based Feature extraction and sparse learning based feature classification using SDNN technique. The identification of the kidney Abnormality in the image is displayed with colour for easy identification and visibility in monitor using HDL algorithms. The design and implementation in real time on both field programmable gate array (FPGA) using Xilinx System Generator (XSG) and Matlab 2013a.
This work presents an embedded hardware architecture for real-time ultrasonic NDE applications that incorporate Hidden Markov Model (HMM) based statistical signal methods. Proposed algorithm is a combination of Discre...
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ISBN:
(纸本)9781538633830
This work presents an embedded hardware architecture for real-time ultrasonic NDE applications that incorporate Hidden Markov Model (HMM) based statistical signal methods. Proposed algorithm is a combination of Discrete Wavelet Transform (DWT) for pre-processing A-scan signals and HMM for classification of the flaw presence. For this study, a MicroZed FPGA with Xilinx Zynq-7020 System-on-Chip (SoC) is chosen for the hardware implementation. A hardware/software approach is used for maximizing the resource usage and efficiency. Wavelet transform has been implemented on the ARM CPU core while the HMM has been implemented on FPGA fabric. Results confirm that the algorithm is feasible for real-time implementation on this low-cost SoC, with an execution time under 40ms.
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