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检索条件"主题词=Field Programmable Gate array"

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FPGA Development in ATE 53

FPGA Development in ATE

引用

IEEE AUTOTESTCON Conference

作者： Hu, Shawn Teradyne Syst Test Grp Def & Aerosp North Reading MA 01864 USA

ISBN: (纸本)9781509049226

In recent years, synthetic test instruments have become increasingly popular in the automatic test equipment (ATE) market. This type of instrument gives users the ability to create custom solutions to better meet their test requirements. FPGA (field programmable gate array) based solutions are the most common synthetic test instrument on the market today. FPGA based solutions can work well due to their inherent flexibility and programmability. They offer high bandwidth outputs and scalable design components, and the design can be easily maintained or transported. The portability of FPGA based solutions is especially advantageous in cases where designs must be maintained over long periods of time, as they can be transferred between test instruments as those are changed or upgraded. However, FPGA design can be complicated and requires increased initial investment. When compared with traditional general-purpose test instruments, the development period tends to be longer. Additionally, while implementing FPGA designs may seem similar to software programming, it requires a different set of skills. To alleviate some of these technical hurdles and to speed up the initial development process, instrument manufacturers offer various solutions to guide the development and ease the implementation process. Test engineers should be aware of the specific complexities that exist for successfully developing FPGA based solutions, how these are offset by the benefits, and how each can be mitigated using appropriate strategies. As an example, using hardware description language (HDL) requires a learning curve, but results in improved portability. If long term maintenance of the test program is critical, HDL designs can be easily transferred from obsolete instruments to new instruments with next generation FPGAs. Though HDL is one of several development methodologies that can be used, the scope of this paper will be limited to examples using HDL. Aspects of initial setup, interfacing wi

关键词： FPGA field programmable gate array Synthetic Instrument HDL

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Side-channel Resistant Soft Core Processor for Lightweight Block Ciphers

Side-channel Resistant Soft Core Processor for Lightweight B...

引用

International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Diehl, William Abdulgadir, Abubakr Kaps, Jens-Peter Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9781538637975

Lightweight cryptographic algorithms which provide moderate security at low cost, especially in very-light power-, energy, and resource-constrained processors, are an important topic of research in the context of the Internet of Things (IoT). Current cryptographic contests and standardization efforts seek to evaluate side-channel resistance of lightweight ciphers on multiple platforms, including resource-constrained 8-bit microprocessors. Using a custom-designed reconfigurable soft core processor on an FPGA, we implement four ciphers, SIMON, PRESENT, LED, and TWINE, and evaluate them for vulnerability to differential power analysis (DPA) using the t-test leakage detection methodology and an open-source test bench (FOBOS). We then adapt and modify techniques used in previous cipher hardware implementations to protect the soft core processor against 1st order DPA. Improved resistance to DPA is verified using the t-test and the FOBOS test bench. No modifications to cipher source code are required for the protected soft core, meaning that software programmers are insulated from the requirement to learn side-channel resistance techniques. A single DPA-resistant soft core instance, which can load and protect all four ciphers simultaneously (where target cipher is selected by the user at run-time), uses 392 slices in the Virtex-7 FPGA - an average of 98 slices per protected cipher.

关键词： Cryptography side channel attack field programmable gate array reconfigurable microcontroller t-test

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An FPGA Oprimization of a Multiple Resolution Architecture for LDR to HDR Image Conversion

An FPGA Oprimization of a Multiple Resolution Architecture f...

引用

International Symposium on Signals, Circuits and Systems (ISSCS)

作者： Cappetta, Carmine Licciardo, Gian Domenico Di Benedetto, Luigi Univ Salerno Dept Ind Engn Via Giovanni Paolo 2 132 I-84084 Fisciano SA Italy

ISBN: (纸本)9781538606742

An architecture capable of performing the inverse Tone Mapping to convert a Low Dynamic Range image into a High Dynamic Range one is proposed. The proposed image processor is specifically designed for a field programmable gate array implementation. The design exploits the presence of specific blocks in the field programmable Logic board, dedicated to the implementation of memories, in order to develop an efficient implementation to process images having a resolution up to 4K UHDTV. The proposed implementation is developed avoiding frame buffers to obtain a design showing low power and a reduced area, in addition to a real-time processing of the image up to Full-HD frames. The proposed scheme achieves state-of-the-art performances and is a lot more flexible than previously developed single resolution architectures.

关键词： inverse Tone Mapping HDR image processing field programmable gate array

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DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications 2017

DTP: Enabling Exhaustive Exploration of FPGA Temporal Partit...

引用

8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Koraei, Mostafa Jahre, Magnus Fatemi, S. Omid Univ Tehran Tehran Iran NTNU Trondheim Norway

ISBN: (纸本)9781450353168

Reconfigurable computing systems show great promise for accelerating streaming HPC applications because of their low power consumption and high performance. However, mapping an HPC application to a reconfigurable system is a challenging task. The challenge is exacerbated by need to temporally partition computational kernels when application requirements exceed resource availability. In this paper, we propose a novel design methodology that we call Data-flow Temporal Partitioning (DTP). The key insight in the design of DTP was that the application should be represented as a high-level data flow graph where each node is a computational kernel and the edges represent inter-node data flow. DTP also supports parallel instantiation of kernels and multiple kernel implementations at different performance/area design points. In contrast to previous proposals, DTP is able to exhaustively explore the solution space for practical applications. Our evaluation of DTP shows that it is able to identify candidate implementations that outperform both previously proposed partitioning heuristics and a direct mapping to the synthesis tool. The temporal configuration selected by DTP can outperform the direct mapping by up to 3X.

关键词： High performance computing field programmable gate array Data flow graph Temporal partitioning Design space exploration

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An Efficient FPGA-Based Architecture for Convolutional Neural Networks 40

An Efficient FPGA-Based Architecture for Convolutional Neura...

引用

40th International Conference on Telecommunications and Signal Processing (TSP)

作者： Hwang, Wen-Jyi Jhang, Yun-Jie Tai, Tsung-Ming Natl Taiwan Normal Univ Dept Comp Sci & Informat Engn Taipei Taiwan

ISBN: (纸本)9781509039821

The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.

关键词： artificial vision systems convolutional neural networks field programmable gate array hardware architecture pipeline operations

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Automation of ATE Test Program Execution in Offline and Online 19

Automation of ATE Test Program Execution in Offline and Onli...

引用

19th IEEE Electronics Packaging Technology Conference (EPTC)

作者： Maria, Deva Ruban Viswanathan, Kamalakannan Amal, Michael Kumar, Karthik Krishna Xilinx Asia Pacific Pte Ltd 5 Changi Business Pk Vista Singapore 486040 Singapore

ISBN: (纸本)9781538630426

Scaling down of transistor nodes gives us the flexibility to pack more complex IP in to one single SOC. The Shrinking technology node enables packaging multiple SOCs on single substrate. That requires higher test coverage, especially in the case of all programmable SOCs and FPGAs. Such higher test coverage requires a sophisticated test program to handle multiple package and grade flavors targeting different user requirements (Industrial, Commercial, Automotive, and Military etc.) under a single test flow. FPGA technology unlike ASIC is 100% programmable and hence before executing any functional test, it needs to be configured for the intended functionality check. This configuration step is unique to FPGA technology and requires appropriate test time. Wafer Sort and Final Test are the two essential test insertions which ensure the products meet the requirements of standard specifications. It's the test engineer's responsibility to develop, validate and release these complex test programs (for both WS & FT) to support FPGA production testing. With the Time to Market (TTM) of products becoming more competitive, it is necessary for the test engineers to explore innovative methods to validate the effectiveness of their test programs. The Test equipment's are so expensive that the semiconductor testing factories only have a limited number of engineering tester hours. [GRAPHICS] . This paper intends to introduce a concept of Offline Sequencer Engine [O.S.E] (Figure 1), which is an automated way of loading, executing the Test programs and saving the test data for the multiple program, package and grade combination in a sequential manner as defined by the user. These data's will be crunched automatically to display the test program changes with its reference program to the test engineers. The OSE also helps to validate the test programs integrity using an offline test system (i.e. no actual tester required). Any workstation can be converted into an offline test system. The p

关键词： field programmable gate array System-On-Chip Automated Test Equipment Test Floor Automation Smart Operation

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Adaptive Control Technique for Generator Side Power System Voltage Stability at Wind Power Station 2nd

引用

2nd International Conference on Intelligent Computing and Applications (ICICA)

作者： Nave, M. Presh Priyatharshini, K. Nijandhan, N. Pradeep, S. KCG Coll Technol Dept EEE Madras Tamil Nadu India PA Coll Engn Dept ECE Pollachi India

ISBN: (纸本)9789811016455;9789811016448

Voltage instability and over voltage are one of the main problems in today wind industry. In wind power production system the output is depends upon the nature of source called wind. But that source is not constant one. It may be varying depending upon the climate. Due to that oscillation the output voltage from the generator side is instability. These problems are becoming a more serious concern with the ever-increasing utilization and higher loading of existing transmission systems, particularly with increasing energy wastage, energy demands, and competitive generation and supply requirements. Our aim is to improve power system voltage stability by enhancing generator reactive, active power control and voltage control. Adaptive feedback system along with the HSVC ways to improve power system voltage stability by enhancing generator controls in the wind power station. To solve this problem adaptive exciter system are used which will adjust the load voltage and the system voltage with that of the reference voltage. The generator output voltage is applied to the adaptive exciter controller (AEC) which updates its stability weight value on demand. The design of modules can be done in Xilinx system generator (XSG). The modules that are designed in system generator can be implemented in FPGA.

关键词： Advanced over-excitation limiters High side voltage control Adjustable speed machines Adaptive linear network Adaptive exciter controller Xilinx system generator field programmable gate array

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Event-Driven Stereo Vision Algorithm Based on Silicon Retina Sensors 27

Event-Driven Stereo Vision Algorithm Based on Silicon Retina...

引用

27th International Conference on Radioelektronika (RADIOELEKTRONIKA)

作者： Eibensteiner, Florian Brachtendorf, Hans Georg Scharinger, Josef Upper Austria Univ Appl Sci Softwarepk 11 A-4232 Hagenberg Austria Johannes Kepler Univ Linz Altenberger Str 69 A-4040 Linz Austria

ISBN: (纸本)9781509045914

In this paper a new stereo matching concept for event-driven silicon retinae is presented. The main contribution of the proposed approach is the correlation of incoming events. As a novelty, not only the spatial information is used, but also the time of occurrence of the events as a part of the similarity measure. Stereo matching is used in depth generating camera systems for solving the correspondence problem and for 3D reconstruction of the sensed environment. In fact, using conventionally frame-based cameras, this is a time consuming and computationally expensive task, especially for high frame rates and spatial resolutions. An event-based silicon retina delivers events only on illumination changes and completely asynchronous in time. The sensor provides no frames, but a time-continuous data stream of intensity differences and thus inherently reduces the visual information to a minimum. This paper focuses on an event-based stereo matching algorithm implemented in hardware on a field programmable gate array (FPGA) that allows a reliable matching of the sparse input event data. Furthermore, the approach is compared to other standard frame-based and event driven stereo methods. The results show that the achieved depth map outperforms other algorithms in terms of accuracy and the calculation performance of the hardware architecture is in the range or still higher than state-of-the-art computing platforms.

关键词： Silicon Retina Stereo Vision Event-Based field programmable gate array Hardware Architecture

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A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA 1

A Cost-Effective Dynamic Partial Reconfiguration Implementat...

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1st New Generation of CAS Conference (NGCAS )

作者： Kamaleldin, Ahmed Ahmed, Islam Obeid, Abulfattah M. Shalash, Ahmed Ismail, Yehea Mostafa, Hassan Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt IC Verificat Solut Mentor Graph Cairo Egypt Amer Univ Cairo & Zewail City Sci & Technol Ctr Nanoelect & Devices Cairo Egypt KACST Riyadh Saudi Arabia

ISBN: (纸本)9781509064472

Reconfigurability of field programmable gate array (FPGA) makes it one of the most promising approaches in the implementation of reconfigurable systems. Partitioning the reconfigurable system to many Reconfigurable Modules (RMs) and allocating them into Reconfigurable Regions (RRs) on the FPGA is a challenging task for the system designer. Partitioning choices impact the area efficiency and the time of reconfiguration of the reconfigurable systems. In this paper, different partitioning techniques are studied and evaluated according to their impact on reconfiguration time and the area utilization. Also, a new proposed Dynamic Partial Reconfiguration (DPR) tool flow is presented that automates and optimizes the partitioning procedure based on a graph clustering algorithm, modifies the design's HDL files as per the partitioning results, and implements a routing switch to dynamically change routing between Reconfigurable Regions (RRs) during reconfiguration.

关键词： Design Automation field programmable gate array Dynamic Partial Reconfiguration

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Hardware Realization of Neural Network Based Controller for Autonomous Robot Navigation

Hardware Realization of Neural Network Based Controller for ...

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International Conference on Computing Methodologies and Communication (ICCMC)

作者： Aamer, Najmuddin Ramachandran, S. Vinayaka Mission Univ ECE Dept Salem Tamil Nadu India BTL Inst Technol ECE Dept Bangalore Karnataka India SJB Inst Technol Elect & Commun Engn Dept Bangalore Karnataka India

ISBN: (纸本)9781509048908

Recently soft computing techniques and artificial intelligent techniques such as fuzzy logic Artificial Neural Network are widely used for variety of systems, namely, controller architecture, pattern learning, navigation etc. This paper describes an alternative hardware solution realized on FPGAs for autonomous mobile robot to avoid obstacles and plan path to reach the target. Pipelined based Artificial Neural Network based controller architecture is proposed using FPGA. The proposed ANN algorithm is able to perform the task for unstructured environment and diverse environments. Simulation and hardware implementation has been done by using Xilinx ISE simulator targeted on Virtex -IV kit. Experimental study shows that proposed approach obtains 357.5 MHz clock frequency which shows improved performance when compared with state-of-art techniques. Similarly, proposed approach shows a significant performance improvement in terms of power consumption.

关键词： Autonomous Mobile Robot Neural Network Path Planning Obstacle Avoidance field programmable gate array Soft Computing

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