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作者： Grace ZGHEIB ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE

学位级别：博士

The design and development of innovative FPGA architectures hinge on the flexibility of its toolchain. Retargetable toolchains, like the Verilog-to-Routing (VTR) flow, have been developed to enable the testing of new FPGAs by mapping circuits onto easily-described and possibly theoretical architectures. However, in reality, the difficulty extends beyond having CAD tools that support the architectural changes: it is equally important for FPGA architects to be able to produce reliable delay and area models for these tools. In addition to having acute architectural intuitions, designing and optimizing the circuit at the transistor-level requires architects to have, as well, a particular set of electrical engineering skills and expertise. The process is also painstaking and time-consuming, rendering the comparison of a variety of architectures or the exploration of a wide design space quite complicated and even impossible in practice. In this work, we present a novel approach to model the delay and area of FPGA architectures with various structures and characteristics, quickly and with acceptable accuracy. ing from the user the transistor-level design and optimization that normally accompany the model- ing process, this approach, called F PRESSO, can be used by any architect without prerequisites. We take inspiration from the way a standard-cell flow performs large-scale transistor-size optimization and apply the same concepts to FPGAs, only at a coarser granularity. Skilled designers prepare for F PRESSO a set of locally optimized libraries of basic parameterizable components with a variety of drive strengths. Then, inexperienced users specify arbitrary FPGA architectures as interconnects of these basic components. The architecture is globally optimized, within minutes, through a standard logic synthesis tool, by choosing the most fitting version of each cell and adding buffers wherever appropriate. The resulting delay and area characteristics are automatically returne

关键词： field programmable gate array FPGA architecture design architecture modeling transistor design architectural exploration F PRESSO wireload modeling CAD tools

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DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications 2017

DTP: Enabling Exhaustive Exploration of FPGA Temporal Partit...

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8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Koraei, Mostafa Jahre, Magnus Fatemi, S. Omid Univ Tehran Tehran Iran NTNU Trondheim Norway

ISBN: (纸本)9781450353168

Reconfigurable computing systems show great promise for accelerating streaming HPC applications because of their low power consumption and high performance. However, mapping an HPC application to a reconfigurable system is a challenging task. The challenge is exacerbated by need to temporally partition computational kernels when application requirements exceed resource availability. In this paper, we propose a novel design methodology that we call Data-flow Temporal Partitioning (DTP). The key insight in the design of DTP was that the application should be represented as a high-level data flow graph where each node is a computational kernel and the edges represent inter-node data flow. DTP also supports parallel instantiation of kernels and multiple kernel implementations at different performance/area design points. In contrast to previous proposals, DTP is able to exhaustively explore the solution space for practical applications. Our evaluation of DTP shows that it is able to identify candidate implementations that outperform both previously proposed partitioning heuristics and a direct mapping to the synthesis tool. The temporal configuration selected by DTP can outperform the direct mapping by up to 3X.

关键词： High performance computing field programmable gate array Data flow graph Temporal partitioning Design space exploration

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Project ELSA: Europa lander for science acquisition 55

Project ELSA: Europa lander for science acquisition

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55th AIAA Aerospace Sciences Meeting

作者： Combs, Darren Frank, Gabriel Grandone, Sara Hall, Colton Johnson, Daniel Luke, Trevor Mende, Scott Nowicki, Daniel Stringer, Benjamin Department of Aerospace Engineering University of Colorado BoulderCO United States

ISBN: (数字)9781624104473

ISBN: (纸本)9781624104473

Jupiter’s moon Europa is of great interest to the scientific community as evidence suggests there may be a deep liquid water ocean beneath its icy surface. To investigate the surface and subsurface, future missions to Europa will require the use of landers and/or surface probes to measure surface characteristics and investigate the potentially unique subsurface conditions beneath the ice. Ball Aerospace has begun to explore the feasibility of conducting an exploration with several small, relatively inexpensive probes as an alternative to a large and costly lander. Our team of nine undergraduate students has designed and constructed a compact, low-cost, spherical probe, which can collect, store, and transmit scientific data relevant to the study of Europa. The goal of our project was to develop and construct a TRL 4 prototype over the course of 8 months, while keeping the cost under $5000. The development focused on data collection, FPGA software development, and system integration while neglecting environmental elements, such as temperature, radiation, and shocks. Two relevant scientific instruments, a triaxial magnetometer and a Geiger counter, were selected and integrated with an avionics package, which is centered on FPGA-based command and data handling (C&DH). The FPGA is integrated with a transceiver to communicate over RF to a ground station, simulating a Europa orbiter. In order to provide the capability to observe magnetic field and radiation variations during one complete orbit of Europa about Jupiter (85 Earth hours), an independent power system was developed and integrated to sustain the probe through its entire mission of 100 hours. The power system, avionics package, science instruments, and transceiver are mounted to a custom-designed structure, contained within a 25.4 centimeter diameter sphere. The prototype collects data for a total of 100 hours, and transmits that data in 8 minute simulated passes, demonstrating the feasibility of using small, cost

关键词： Europa Avionics Systems field programmable gate array Ground Station Transceiver Magnetometers Power System Earth Software Development Moon

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Flexible FPGA based hardware in the loop simulator for control, fault-tolerant and cyber-physical systems 55

Flexible FPGA based hardware in the loop simulator for contr...

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55th AIAA Aerospace Sciences Meeting

作者： Bakker, Tim Leccadito, Matthew T. Klenke, Robert H. Virginia Commonwealth University Electrical and Computer Engineering RichmondVA23220 United States

ISBN: (数字)9781624104473

ISBN: (纸本)9781624104473

Hardware In the Loop Simulation (HILS) is a development platform wherein the real hardware/software system is thoroughly tested and verified for proper working within a simulation environment. The use of HILS can significantly reduce the cost of developing and testing a complex control system where the physical environment cannot be easily reproduced or where a failure could have a costly or even catastrophic effect (ie. aerospace or automotive industries). This paper describes a field programmable gate array (FPGA) based modular HILS platform for unmanned systems with the ability to inject sensor failures and deploy Cyber-Physical System (CPS) attacks. The proposed platform is ideally suited for the development and testing of fault-tolerant cyber-secure control systems. The implemented HILS platform is demonstrated using an existing Flight Control System (FCS) for small Unmanned Aerial Systems (sUAS). © 2017 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

关键词： field programmable gate array Cyber Physical System Barometric Pressure Sensor Flight Control System Control Systems Hardware in the Loop Simulation Unmanned System Unmanned Aerial Systems Ground Control Station Ground Communication System

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Synthesizable Assertion in Hardware and Software Development 2017

Synthesizable Assertion in Hardware and Software Development

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Proceedings of the International Conference on Imaging, Signal Processing and Communication

作者： Ooi Ruey Hock Zulfiqar Ali Bin Abd.Aziz J-Wing Teh University Sains Malaysia Intel Corporation(M) Sdn.Bhd.

ISBN: (纸本)9781450352895

Assertion Based Validation(ABV) is an approach in which the design intent is captured in an executable form where all the out of range and missing intent intents will trigger an error which indicates the fall-outs. By using these assertions can enable early detection of very basic software and hardware bugs in the design. System Verilog is a hardware description language that combine with verification and commonly used as assertion language with its powerful assertion function embedded in the language itself. However not all system verilog language can be synthesize into hardware component and because of the limitation, it only use in software simulation phase of a design cycle. The approach to enable the ABV module in system verilog format to be synthesized into a portion of the hardware is the intent of this paper. It defines the synthesizable building blocks of the assertion modules. This can utilized by both hardware and software development in pre-silicon stage through reconfigurable hardware or field programmable gate array(FPGA). In hardware debug, the synthesized assertions will point to the area of failure, reducing the scope of debug. In software development, the synthesized assertions will point to invalid configurations of hardware registers. The assertions will be synthesized into a separate hardware block which is programmed into a reconfigurable hardware or FPGA together with the Design-Under-Test(DUT). The assertion validation hardware block consists of a ‘Detection and Distribution' block and a series of ‘Property Tracking' block to track the multiple events separately. If all separate events are met but the expected scenario is not met, a register bit will be set for this assertion point to signify failure. Final assertion results will be written to memory on the reconfigurable hardware or FGPA. The purpose of this paper is to identify the common assertion function that widely use in hardware design and synthesis of these assertion properties from

关键词： Assertion Based Validation, ABV System Verilog field programmable gate array FPGA

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An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation 17

An Energy-Efficient Design-Time Scheduler for FPGAs Leveragi...

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ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Loke, Wei Ting Koay, Chin Yang Natl Univ Singapore Singapore Singapore Xilinx San Jose CA USA

ISBN: (纸本)9781450343541

We present a design-time tool, EASTA, that combines the feature of reconfigurability in FPGAs and Dynamic Frequency Scaling to realize an efficient multiprocessing scheduler on a single-FPGA system. Multiple deadlines, reconvergent nodes, flow dependency and processor constraints of the multiprocessor problem on general task graphs are rigorously taken into consideration. EASTA is able to determine the minimum number of processing elements required to create a feasible schedule and dynamically adjust the clock speed of each processing element to reclaim slack. The schedule is represented by an efficient tree-based lookup table. We evaluate the EASTA tool using randomly generated task graphs and demonstrate that our framework is able to produce energy savings of 39.41% and 33% for task graphs of size 9.

关键词： field programmable gate array Low Power Dynamic Frequency Scaling Design-Time Scheduling

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DEVELOPMENT OF A SOFTWARE-DEFINED GNSS SIMULATION PROTOTYPE FOR ADVANCED SIGNALS RESEARCH

DEVELOPMENT OF A SOFTWARE-DEFINED GNSS SIMULATION PROTOTYPE ...

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作者： Michael J. Ledford Air Force Institute of Technology

学位级别：硕士

Global Positioning System (GPS) has become the de-facto standard for precision time transfer. By definition, all signal structure details of the open civilian GPS signals are known and published. This makes them vulnerable to a growing array of threats. One possible solution is to incorporate signal authentication features for future GPS. However, there lacks a hardware platform to verify these features. This thesis proposes a field programmable gate array (FPGA)-based GPS Waveform Prototyping Platform (GWPP) that features a software-defined all-digital signal syn- thesis architecture in conjunction with a high-speed Digital-to-Analog Converter as a solution. GWPP is designed to synthesize GPS waveforms based on the emerging and ma- turing signal generation technology known as Direct Digital Synthesis (DDS). DDS adds dimensions not possible with analog designs in the sense that the fundamen- tal nature of the waveform and its features are generated digitally; hence, providing precise control over the amplitude, frequency, phase, and modulation scheme of the output waveform. The goal of this research is to design, implement, and integrate the GWPP ar- chitecture into the Virtex R? -6 FPGA framework. The limited resources in the FPGA presents a trade-off between signal quality and FPGA resource utilization. This work not only explores the feasibility of the DDS-based architecture to synthesize GPS waveforms, namely the Link-1 Course Acquisition (L1 C/A) signal, but also assesses the spectral performance with consideration in FPGA resource utilization. Currently, the architecture achieves a spurious free dynamic range (SFDR) of -46 decibels rela- tive to the carrier (dBc) consuming only 10% of FPGA logic slices.

关键词： Global Positioning System GPS Global Navigation Satellite System GNSS field programmable gate array FPGA Software-Defined Direct Digital Synthesis DDS

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A Fast and Accurate FPGA System for Short Read Mapping Based on Parallel Comparison on Hash Table

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2017年第5期E100D卷 1016-1025页

作者： Sogabe, Yoko Maruyama, Tsutomu Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki 3058573 Japan

The purpose of DNA sequencing is to determine the order of nucleotides within a DNA molecule of target. The target DNA molecules are fragmented into short reads, which are short fixed-length subsequences composed of 'A', 'C', 'G' 'T', by next generation sequencing (NGS) machine. To reconstruct the target DNA from the short reads using a reference genome, which is a representative example of a species that was constructed in advance, it is necessary to determine their locations in the target DNA from where they have been extracted by aligning them onto the reference genome. This process is called short read mapping, and it is important to improve the performance of the short read mapping to realize fast DNA sequencing. We propose three types of FPGA acceleration methods based on hash table;(1) sorting and parallel comparison, (2) matching that allows one mutation to reduce the number of the candidates, (3) optimized hash function using variable masks. The first one reduces the number of accesses to off-chip memory to avoid the bottleneck by access latency. The second one enables to reduce the number of the candidates without degrading mapping sensitivity by allowing one mutation in the comparison. The last one reduces hash collisions using a table that was calculated from the reference genome in advance. We implemented the three methods on Xilinx Virtex-7 and evaluated them to show their effectiveness of them. In our experiments, our system achieves 20 fold of processing speed compared with BWA, which is one of the most popular mapping tools. Furthermore, we shows that the our system outperforms one of the fastest FPGA short read mapping systems.

关键词： field programmable gate array genome sequence alignment accelerated implementation bioinformatics

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FPGA-based SOC for hardware implementation of a local histogram-based video shot detector

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2017年第4期25卷 3300-3318页

作者： Ben Abdelali, Abdessalem Krifa, Mohamed Nidhal Mtibaa, Abdellatif Univ Monastir Lab Elect & Microelect Monastir Tunisia

In this paper, we present a video application example and its implementation in a reconfigurable system-on chip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse hardware module versions corresponding to different quantization levels and architectural solutions for an LH-based shot detection system are presented. The developed modules have different hardware resource occupations and can be used in a dynamic way to allow flexible management of the target hardware system. They also show high execution time efficiency and can reach an important bandwidth that can support the most recent high-resolution video formats with a high rate of frames per second. A complete SOC-based demonstration for video summarization based on the LH is also developed. It includes the LH extraction, shot boundary detection, and key frame visualization.

关键词： Hardware implementation field programmable gate array system on chip partial dynamic reconfiguration real time local histogram shot boundary detection video summarization

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Model Predictive Control of an Underactuated Spacecraft with Two Reaction Wheels

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2017年第2期40卷 320-332页

作者： Petersen, Christopher D. Leve, Frederick Kolmanovsky, Ilya Univ Michigan Dept Aerosp Engn Ann Arbor MI 48109 USA US Air Force Res Lab Guidance Nav & Control Grp Albuquerque NM 87117 USA

This paper presents an application of model predictive control to the attitude dynamics of an underactuated spacecraft with two reaction wheels and zero angular momentum. Such a system cannot be stabilized by any smooth or continuous time-invariant feedback law. However, model predictive control has a remarkable ability to generate control laws that are discontinuous in the state and, as such, can be applied to this problem. The model predictive control formulation is analyzed in depth and shown to produce an asymptotically stabilizing controller, which is discontinuous and enforces constraints. Simulations on the full nonlinear model demonstrate that model predictive control can successfully control the attitude of an underactuated spacecraft when the attitude maneuvers are sufficiently small.

关键词： Spacecraft Attitude Spacecraft Models Model Predictive Control Feedback Control Attitude Stabilization Euler Angles Optimal Control Nonlinear Dynamics field programmable gate array Spacecraft Missions

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