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检索条件"主题词=Field Programmable Gate array"

共 1340 条记录，以下是671-680 订阅

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Comparing the Cost of Protecting Selected Lightweight Block Ciphers Against Differential Power Analysis in Low-Cost FPGAs 16

Comparing the Cost of Protecting Selected Lightweight Block ...

引用

16th IEEE International Conference on field-programmable Technology (ICFPT)

作者： Diehl, William Abdulgadir, Abubakr Kaps, Jens-Peter Gaj, Kris George Mason Univ ECE Dept Fairfax VA 22030 USA

ISBN: (纸本)9781538626566

Lightweight block ciphers are an important topic in the Internet of Things (IoT), since they provide moderate security, while requiring fewer resources than AES. Ongoing cryptographic contests and standardization efforts evaluate lightweight block ciphers on their resistance to power analysis side channel attack (SCA), and the ability to apply countermeasures. While some ciphers have been individually evaluated, a large scale comparison of resistance to side channel attack and formulation of the relative cost of implementing countermeasures is difficult, since researchers typically use varied architectures, optimization strategies, technologies, and evaluation techniques. In this research we leverage the t-test leakage detection methodology and an open-source side channel analysis suite (FOBOS) to compare FPGA implementations of AES, SIMON, SPECK, PRESENT, LED, and TWINE, using a choice of architecture targeted to optimize throughput-to-area (TP/A) ratio, for resistance to differential power analysis (DPA). We then apply an equivalent level of protection to the above ciphers using 3-share threshold implementations (TI), and verify improved resistance to DPA. We find that SIMON has the highest TP/A ratio of protected versions, followed by PRESENT, TWINE, LED, AES, and SPECK. However, PRESENT uses the least energy in terms of nJ-per-bit.

关键词： Cipher cryptography encryption field programmable gate array side channel attack countermeasure

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Circuit Design, Architecture and CAD for RRAM-based FPGAs

Circuit Design, Architecture and CAD for RRAM-based FPGAs

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作者： Xifan TANG ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE

学位级别：博士

field programmable gate arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power on. Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be "Normally powered off, Instantly powered on". Second, by combining functional- ity of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS cir- cuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis, we present high-performance and low-power RRAM-based FPGAs from transistor- level circuit designs to architecture-level optimizations and CAD tools, using theoretical anal- ysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and e

关键词： Resistive Memory field programmable gate array Circuit Design Programming Structure Multiplexer Physical Design Computer-Aided Design

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A Single-character Refreshable Braille Display with FPGA Control 5th

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5th International Conference on Advancements of Medicine and Health Care through Technology (MEDITECH)

作者： Ignat, M. C. Farago, P. Hintea, S. Roman, M. N. Vlad, S. Tech Univ Cluj Napoca Bases Elect Dept Cluj Napoca Romania Tech Univ Cluj Napoca Electrotech & Measurements Dept Cluj Napoca Romania

ISBN: (纸本)9783319528755;9783319528748

Visual impairment, in terms of sight loss and blindness, affects 285 million people worldwide. While 80% of the cases are either treatable or preventable, the remainder require alternative means to compensate limitations in mobility, reading, communication, access technology, etc. For this purpose, braille is an alphabet used by the visually impaired for tactile reading. Refreshable braille displays are electromechanical devices used for the electronic display of braille characters. This paper presents a one-character refreshable braille display, implemented with electromagnetic relays and control logic implemented on a field programmable gate array (FPGA). The advantage of one-character braille display is that it enables static reading, which contributes to user comfort. From a technical point of view, one-character braille display requires a reduced number of electromechanical components. This allows a smaller size of the display device, as well as reduced costs. On the other hand, FPGA control exhibits several advantages in terms of ease of use and parallel processing. Experiments demonstrate the functionality of the proposed braille display device.

关键词： Refreshable braille display electromechanical relay field programmable gate array

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Approach to the FPGA-based Self-configurable Computer Systems Support Using Unix-like Operation System 14

Approach to the FPGA-based Self-configurable Computer System...

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14th International Conference on the Experience of Designing and Application of CAD Systems in Microelectronics (CADSM)

作者： Melnyk, Viktor Kit, Andrii Lviv Polytech Natl Univ Dept Informat Technol Secur S Bandery Str 12 Lvov Ukraine John Paul II Catholic Univ Lublin Fac Math IT & Landscape Architecture Konstantynow 1H Lublin Poland

ISBN: (纸本)9781509050451

The questions of further implementation of the operating system software means for the FPGA-based self-configurable computer systems support discussed in the paper. An approach for the FPGA-based self-configurable computer systems support using Unix-like OS presented. According proposed approach in the self-configurable computer systems (SCCS) the labor-intensive and time-consuming works of tasks distribution between the processing units and development of the IP cores required for implementation in the RCE, are fully automated on the software level and replaced from the operator to the computer system.

关键词： self-configurable computer system operating system field programmable gate array high-performance computing reconfigurable computing

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Leading the Blind: Automated Transistor-Level Modeling for FPGA Architects

Leading the Blind: Automated Transistor-Level Modeling for F...

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作者： Grace ZGHEIB ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE

学位级别：博士

The design and development of innovative FPGA architectures hinge on the flexibility of its toolchain. Retargetable toolchains, like the Verilog-to-Routing (VTR) flow, have been developed to enable the testing of new FPGAs by mapping circuits onto easily-described and possibly theoretical architectures. However, in reality, the difficulty extends beyond having CAD tools that support the architectural changes: it is equally important for FPGA architects to be able to produce reliable delay and area models for these tools. In addition to having acute architectural intuitions, designing and optimizing the circuit at the transistor-level requires architects to have, as well, a particular set of electrical engineering skills and expertise. The process is also painstaking and time-consuming, rendering the comparison of a variety of architectures or the exploration of a wide design space quite complicated and even impossible in practice. In this work, we present a novel approach to model the delay and area of FPGA architectures with various structures and characteristics, quickly and with acceptable accuracy. ing from the user the transistor-level design and optimization that normally accompany the model- ing process, this approach, called F PRESSO, can be used by any architect without prerequisites. We take inspiration from the way a standard-cell flow performs large-scale transistor-size optimization and apply the same concepts to FPGAs, only at a coarser granularity. Skilled designers prepare for F PRESSO a set of locally optimized libraries of basic parameterizable components with a variety of drive strengths. Then, inexperienced users specify arbitrary FPGA architectures as interconnects of these basic components. The architecture is globally optimized, within minutes, through a standard logic synthesis tool, by choosing the most fitting version of each cell and adding buffers wherever appropriate. The resulting delay and area characteristics are automatically returne

关键词： field programmable gate array FPGA architecture design architecture modeling transistor design architectural exploration F PRESSO wireload modeling CAD tools

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Project ELSA: Europa lander for science acquisition 55

Project ELSA: Europa lander for science acquisition

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55th AIAA Aerospace Sciences Meeting

作者： Combs, Darren Frank, Gabriel Grandone, Sara Hall, Colton Johnson, Daniel Luke, Trevor Mende, Scott Nowicki, Daniel Stringer, Benjamin Department of Aerospace Engineering University of Colorado BoulderCO United States

ISBN: (数字)9781624104473

ISBN: (纸本)9781624104473

Jupiter’s moon Europa is of great interest to the scientific community as evidence suggests there may be a deep liquid water ocean beneath its icy surface. To investigate the surface and subsurface, future missions to Europa will require the use of landers and/or surface probes to measure surface characteristics and investigate the potentially unique subsurface conditions beneath the ice. Ball Aerospace has begun to explore the feasibility of conducting an exploration with several small, relatively inexpensive probes as an alternative to a large and costly lander. Our team of nine undergraduate students has designed and constructed a compact, low-cost, spherical probe, which can collect, store, and transmit scientific data relevant to the study of Europa. The goal of our project was to develop and construct a TRL 4 prototype over the course of 8 months, while keeping the cost under $5000. The development focused on data collection, FPGA software development, and system integration while neglecting environmental elements, such as temperature, radiation, and shocks. Two relevant scientific instruments, a triaxial magnetometer and a Geiger counter, were selected and integrated with an avionics package, which is centered on FPGA-based command and data handling (C&DH). The FPGA is integrated with a transceiver to communicate over RF to a ground station, simulating a Europa orbiter. In order to provide the capability to observe magnetic field and radiation variations during one complete orbit of Europa about Jupiter (85 Earth hours), an independent power system was developed and integrated to sustain the probe through its entire mission of 100 hours. The power system, avionics package, science instruments, and transceiver are mounted to a custom-designed structure, contained within a 25.4 centimeter diameter sphere. The prototype collects data for a total of 100 hours, and transmits that data in 8 minute simulated passes, demonstrating the feasibility of using small, cost

关键词： Europa Avionics Systems field programmable gate array Ground Station Transceiver Magnetometers Power System Earth Software Development Moon

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DEVELOPMENT OF A SOFTWARE-DEFINED GNSS SIMULATION PROTOTYPE FOR ADVANCED SIGNALS RESEARCH

DEVELOPMENT OF A SOFTWARE-DEFINED GNSS SIMULATION PROTOTYPE ...

引用

作者： Michael J. Ledford Air Force Institute of Technology

学位级别：硕士

Global Positioning System (GPS) has become the de-facto standard for precision time transfer. By definition, all signal structure details of the open civilian GPS signals are known and published. This makes them vulnerable to a growing array of threats. One possible solution is to incorporate signal authentication features for future GPS. However, there lacks a hardware platform to verify these features. This thesis proposes a field programmable gate array (FPGA)-based GPS Waveform Prototyping Platform (GWPP) that features a software-defined all-digital signal syn- thesis architecture in conjunction with a high-speed Digital-to-Analog Converter as a solution. GWPP is designed to synthesize GPS waveforms based on the emerging and ma- turing signal generation technology known as Direct Digital Synthesis (DDS). DDS adds dimensions not possible with analog designs in the sense that the fundamen- tal nature of the waveform and its features are generated digitally; hence, providing precise control over the amplitude, frequency, phase, and modulation scheme of the output waveform. The goal of this research is to design, implement, and integrate the GWPP ar- chitecture into the Virtex R? -6 FPGA framework. The limited resources in the FPGA presents a trade-off between signal quality and FPGA resource utilization. This work not only explores the feasibility of the DDS-based architecture to synthesize GPS waveforms, namely the Link-1 Course Acquisition (L1 C/A) signal, but also assesses the spectral performance with consideration in FPGA resource utilization. Currently, the architecture achieves a spurious free dynamic range (SFDR) of -46 decibels rela- tive to the carrier (dBc) consuming only 10% of FPGA logic slices.

关键词： Global Positioning System GPS Global Navigation Satellite System GNSS field programmable gate array FPGA Software-Defined Direct Digital Synthesis DDS

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Flexible FPGA based hardware in the loop simulator for control, fault-tolerant and cyber-physical systems 55

Flexible FPGA based hardware in the loop simulator for contr...

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55th AIAA Aerospace Sciences Meeting

作者： Bakker, Tim Leccadito, Matthew T. Klenke, Robert H. Virginia Commonwealth University Electrical and Computer Engineering RichmondVA23220 United States

ISBN: (数字)9781624104473

ISBN: (纸本)9781624104473

Hardware In the Loop Simulation (HILS) is a development platform wherein the real hardware/software system is thoroughly tested and verified for proper working within a simulation environment. The use of HILS can significantly reduce the cost of developing and testing a complex control system where the physical environment cannot be easily reproduced or where a failure could have a costly or even catastrophic effect (ie. aerospace or automotive industries). This paper describes a field programmable gate array (FPGA) based modular HILS platform for unmanned systems with the ability to inject sensor failures and deploy Cyber-Physical System (CPS) attacks. The proposed platform is ideally suited for the development and testing of fault-tolerant cyber-secure control systems. The implemented HILS platform is demonstrated using an existing Flight Control System (FCS) for small Unmanned Aerial Systems (sUAS). © 2017 by the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

关键词： field programmable gate array Cyber Physical System Barometric Pressure Sensor Flight Control System Control Systems Hardware in the Loop Simulation Unmanned System Unmanned Aerial Systems Ground Control Station Ground Communication System

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Synthesizable Assertion in Hardware and Software Development 2017

Synthesizable Assertion in Hardware and Software Development

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Proceedings of the International Conference on Imaging, Signal Processing and Communication

作者： Ooi Ruey Hock Zulfiqar Ali Bin Abd.Aziz J-Wing Teh University Sains Malaysia Intel Corporation(M) Sdn.Bhd.

ISBN: (纸本)9781450352895

Assertion Based Validation(ABV) is an approach in which the design intent is captured in an executable form where all the out of range and missing intent intents will trigger an error which indicates the fall-outs. By using these assertions can enable early detection of very basic software and hardware bugs in the design. System Verilog is a hardware description language that combine with verification and commonly used as assertion language with its powerful assertion function embedded in the language itself. However not all system verilog language can be synthesize into hardware component and because of the limitation, it only use in software simulation phase of a design cycle. The approach to enable the ABV module in system verilog format to be synthesized into a portion of the hardware is the intent of this paper. It defines the synthesizable building blocks of the assertion modules. This can utilized by both hardware and software development in pre-silicon stage through reconfigurable hardware or field programmable gate array(FPGA). In hardware debug, the synthesized assertions will point to the area of failure, reducing the scope of debug. In software development, the synthesized assertions will point to invalid configurations of hardware registers. The assertions will be synthesized into a separate hardware block which is programmed into a reconfigurable hardware or FPGA together with the Design-Under-Test(DUT). The assertion validation hardware block consists of a ‘Detection and Distribution' block and a series of ‘Property Tracking' block to track the multiple events separately. If all separate events are met but the expected scenario is not met, a register bit will be set for this assertion point to signify failure. Final assertion results will be written to memory on the reconfigurable hardware or FGPA. The purpose of this paper is to identify the common assertion function that widely use in hardware design and synthesis of these assertion properties from

关键词： Assertion Based Validation, ABV System Verilog field programmable gate array FPGA

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An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation 17

An Energy-Efficient Design-Time Scheduler for FPGAs Leveragi...

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ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Loke, Wei Ting Koay, Chin Yang Natl Univ Singapore Singapore Singapore Xilinx San Jose CA USA

ISBN: (纸本)9781450343541

We present a design-time tool, EASTA, that combines the feature of reconfigurability in FPGAs and Dynamic Frequency Scaling to realize an efficient multiprocessing scheduler on a single-FPGA system. Multiple deadlines, reconvergent nodes, flow dependency and processor constraints of the multiprocessor problem on general task graphs are rigorously taken into consideration. EASTA is able to determine the minimum number of processing elements required to create a feasible schedule and dynamically adjust the clock speed of each processing element to reclaim slack. The schedule is represented by an efficient tree-based lookup table. We evaluate the EASTA tool using randomly generated task graphs and demonstrate that our framework is able to produce energy savings of 39.41% and 33% for task graphs of size 9.

关键词： field programmable gate array Low Power Dynamic Frequency Scaling Design-Time Scheduling

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