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Real-time fiber Bragg grating measurement system using temperature-controlled Fourier domain mode locking laser

OPTICAL ENGINEERING 2017年第6期56卷 066112-066112页

作者： Yamaguchi, Tatsuya Shinoda, Yukitaka Nihon Univ Grad Sch Sci & Technol Elect Engn Chiyoda Ku Tokyo Japan Nihon Univ Coll Sci & Technol Elect Engn Chiyoda Ku Tokyo Japan

We constructed a temperature-controlled Fourier domain mode locking (TC-FDML) laser capable of high-speed wavelength sweeping and developed a real-time fiber Bragg grating (FBG) measurement system. The TC-FDML laser can perform high-speed wavelength sweeping at a sweep frequency of 50.7 kHz with a scan range of similar to 60 nm in the 1.55-mu m band. This system uses a data acquisition system mounting an analog/digital converter and field programmable gate array that enables real-time FBG measurement at a sampling frequency of 250 MHz. Using bidirectional wavelength sweeping by the TC-FDML laser, the system has a measurement time resolution of 9.9 mu s. We show that the developed system can measure high-speed vibrations of several kHz and perform simultaneous and continuous measurements of multiple FBGs for a period of one hour. (C) The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License.

关键词： fiber Bragg grating temperature-controlled Fourier domain mode locking laser real-time measurement vibration measurement wavelength-swept laser field programmable gate array

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Digital-Analog Hybrid Scheme and Its Application to Chaotic Random Number Generators

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INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS 2017年第14期27卷 1750210-1750210页

作者： Yuan, Zeshi Li, Hongtao Miao, Yunchi Hu, Wen Zhu, Xiaohua Nanjing Univ Sci & Technol Sch Elect & Opt Engn Nanjing 210094 Jiangsu Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Elect & Informat Engn Nanjing 210094 Jiangsu Peoples R China

Practical randomnumber generation (RNG) circuits are typically achieved with analog devices or digital approaches. Digital-based techniques, which use field programmable gate array (FPGA) and graphics processing units (GPU) etc. usually have better performances than analog methods as they are programmable, efficient and robust. However, digital realizations suffer from the effect of finite precision. Accordingly, the generated random numbers (RNs) are actually periodic instead of being real random. To tackle this limitation, in this paper we propose a novel digitalanalog hybrid scheme that employs the digital unit as the main body, and minimum analog devices to generate physical RNs. Moreover, the possibility of realizing the proposed scheme with only one memory element is discussed. Without loss of generality, we use the capacitor and the memristor along with FPGA to construct the proposed hybrid system, and a chaotic true random number generator (TRNG) circuit is realized, producing physical RNs at a throughput of Gbit/ s scale. These RNs successfully pass all the tests in the NIST SP800-22 package, confirming the significance of the scheme in practical applications. In addition, the use of this new scheme is not restricted to RNGs, and it also provides a strategy to solve the effect of finite precision in other digital systems.

关键词： field programmable gate array finite precision hybrid scheme random number generator NIST

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Bitwise efficiency in chaotic models

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PROCEEDINGS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2017年第2205期473卷 20170144-20170144页

作者： Jeffress, Stephen Duben, Peter Palmer, Tim Univ Oxford Dept Atmospher Phys Oxford England

Motivated by the increasing energy consumption of supercomputing for weather and climate simulations, we introduce a framework for investigating the bit-level information efficiency of chaotic models. In comparison with previous explorations of inexactness in climate modelling, the proposed and tested information metric has three specific advantages: (i) it requires only a single high-precision time series;(ii) information does not grow indefinitely for decreasing time step;and (iii) information is more sensitive to the dynamics and uncertainties of the model rather than to the implementation details. We demonstrate the notion of bit-level information efficiency in two of Edward Lorenz's prototypical chaotic models: Lorenz 1963 (L63) and Lorenz 1996 (L96). Although L63 is typically integrated in 64-bit 'double' floating point precision, we show that only 16 bits have significant information content, given an initial condition uncertainty of approximately 1% of the size of the attractor. This result is sensitive to the size of the uncertainty but not to the time step of the model. We then apply the metric to the L96 model and find that a 16-bit scaled integer model would suffice given the uncertainty of the unresolved sub-grid-scale dynamics. We then show that, by dedicating computational resources to spatial resolution rather than numeric precision in a field programmable gate array (FPGA), we see up to 28.6% improvement in forecast accuracy, an approximately fivefold reduction in the number of logical computing elements required and an approximately 10-fold reduction in energy consumed by the FPGA, for the L96 model.

关键词： information chaos supercomputing inexactness precision field programmable gate array

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REAL-TIME SIMULATION AND VISUALIZATION ARCHITECTURE WITH field programmable gate array (FPGA) SIMULATOR

REAL-TIME SIMULATION AND VISUALIZATION ARCHITECTURE WITH FIE...

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2nd ASME 2010 World Conference on Innovative Virtual Reality

作者： Karkee, Manoj Monga, Madhu Steward, Brian L. Zambreno, Joseph Kelkar, Atul G. Iowa State Univ Dept Agr & Biosyst Engn Ames IA 50011 USA

ISBN: (纸本)9780791849088

Real-time simulation of dynamic vehicle system models is essential to facilitate advances in operator and hardware in the loop simulation and virtual prototyping. Real-time virtual reality-based simulation enables users to visualize and perceive the effect of their actions during the simulation. As model complexity is increased to improve the model fidelity, the computational requirements will also increase, thus increasing the challenge to meet real-time constraints. A distributed simulator architecture was developed for off-road vehicle dynamic models and 3D graphics visualization to distribute the overall computational load across multiple computational platforms. This architecture consisted of three major components: a dynamic model simulator, a virtual reality simulator, and an interface to controller and input hardware devices. The dynamic model simulator component was developed using Matlab/Simulink Real Time Workshop on a PC and also using field programmable gate arrays (FPGA), which offered a highly parallel hardware platform. The simulator architecture reduced the computational load to an individual platform and increased the real-time simulation capability with complex off-road vehicle system models and controllers. The architecture was used to develop, simulate and visualize a tractor and towed implement steering dynamics model. The model also included a steering valve subsystem which contained very high frequency hydraulic dynamics and required 10 mu s integration time step for numerical stability. The real-time simulation goal was not achievable for the model with this level of complexity when the PC-based simulator was used. However, the FPGA-based simulator achieved a real-time goal taking only 2 mu s to complete one integration time step.

关键词： Real-time Simulation Distributed Architecture Virtual Reality Vehicle Dynamics Models field programmable gate array

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Designing and Implementing a Lightweight WSN MAC Protocol for Smart Home Networking Applications

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2017年第3期26卷 1750043-1750043页

作者： Chen, Ching-Han Lin, Ming-Yi Lin, Wen-Hung Natl Cent Univ Dept CSIE Machine Intelligence & Automat Technol MIAT Lab 300 Jhongda Rd Taoyuan 32001 Taiwan

Wireless sensor networks (WSNs) represent a promising solution in the fields of the Internet of Things (IoT) and machine-to-machine networks for smart home applications. However, to feasibly deploy wireless sensor devices in a smart home environment, four key requirements must be satisfied: stability, compatibility, reliability routing, and performance and power balance. In this study, we focus on the unreliability problem of the IEEE 802.15.4 WSN medium access control (MAC), which is caused by the contention-based MAC protocol used for channel access. This problem results in a low packet delivery ratio, particularly in a smart home network with only a few sensor nodes. In this paper, we first propose a lightweight WSN protocol for a smart home or an intelligent building, thus replacing the IEEE 802.15.4 protocol, which is highly complex and has a low packet delivery ratio. Subsequently, we describe the development of a discrete event system model for the WSN by using a GRAFCET and propose a development platform based on a reconfigurable FPGA for reducing fabrication cost and time. Finally, a prototype WSN controller ASIC chip without an extra CPU and with our proposed lightweight MAC was developed and tested. It enhanced the packet delivery ratio by up to 100%.

关键词： field programmable gate array lightweight MAC wireless sensor network ZigBee

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Hybrid multilevel DC link inverter with reduced power electronic switches

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Energy Procedia 2017年 117卷 626-634页

作者： G Durga Prasad V Jegathesan P V V Rama Rao Shri Vishnu Engineering College for Women EEE Dept. Bhimavaram Andhra pradesh 534202 India

The employments of Multilevel DC Link Inverters offer dependable points of interest attributable to the expansion in the highest levels at the yield output voltage and are broadly acknowledged for industrial applications. The execution of these bores on high when contrasted with the routine conventional two-level inverters because of their drawbacks. Be that as it may, the expanded number of devices, complex PWM control, and voltage-adjusting issue are a portion of the hindrances. This paper goes for presenting another topology, which can perilously decrease the switch number by introducing a module called polarity generation module. This topology gives a DC voltage fit as a fiddle of a staircase which approximates the corrected state of a directed sinusoidal wave to the extension inverter, which thusly interchanges the extremity to deliver an AC voltage with low THD and switching loss. The topology is tested by adopting a choice of control techniques and enhanced execution of the proposed inverter contrasted with the overarching topologies. The FPGA has been selected to verify the proposed inverter with modulating technique due its advanced futures and computing facility. For validation, simulation and experimental results are offered.

关键词： field programmable gate array Multilevel DC Link Inverters Pulse Width Modulation sinusoidal pulse width modulation Total Harmonic Distortion

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Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

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IET COMPUTERS AND DIGITAL TECHNIQUES 2016年第2期10卷 59-68页

作者： Venkatachalam, Nithish Kumar Gopalakrishnan, Lakshminarayanan Sellathurai, Mathini Natl Inst Technol Tiruchirappalli Dept Elect & Commun Engn Tiruchirappalli Tamil Nadu India Heriot Watt Univ Sch Engn & Phys Sci Edinburgh Midlothian Scotland

Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. field programmable gate array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attaining the new index is quite complex. In this study, the authors propose a low complexity and area efficient reconfigurable architecture for multimode interleaver address generator to support multiple wireless standards. In addition, a novel MOD_row and MOD_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and 64-QAM modulation schemes under all possible code rates. The reconfigurable address generator for various block size and modulation scheme are implemented on Xilinx Spartan XC3S400 FPGA and the functionalities are verified through simulation. The synthesis results of the proposed design shows a reduction of 60% in resource utilisation and an improvement of 46% in operating frequency over the existing approaches.

关键词： wireless LAN WiMax protocols software radio field programmable gate arrays quadrature phase shift keying quadrature amplitude modulation codes hardware description languages multistandard radios reconfigurable multimode interleaver address generator reconfigurable transceiver complex software defined radio applications physical layer multiple protocols IEEE 802 11a-g standards IEEE 802 16e standards wireless local area network WiMAX wireless standards block interleaving technique two step permutation hardware implementation floor and modulus functions MOD functions field programmable gate array area efficient reconfigurable architecture multiple wireless standards MOD_row MOD_column circuits row counter values column counter values BPSK modulation schemes QPSK schemes 16-QAM schemes 64-QAM schemes code rates Verilog HDL Xilinx Spartan 3 FPGA resource utilisation operating frequency

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High-performance digital replica of analogue peak current mode control for DC-DC converter

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IET POWER ELECTRONICS 2016年第4期9卷 809-816页

作者： Taeed, Fazel Nymand, Morten Univ Southern Denmark Maersk Mc Kinney Moller Inst Fac Engn Odense Denmark

A simple and robust digital peak current mode controller is proposed in this study. The controller replicates an analogue peak current mode control in the discrete domain. The inner current loop has negligible delay, which results in a high controller bandwidth. The controller structure allows the compensation slope to be updated in each switching cycle;therefore, the controller can maintain a high bandwidth over a wide range of operating points. The modelling principles of an analogue peak current mode controller are used to model the proposed controller. For experimental verification, the controller is implemented in a field programmable gate array to control a 100 W buck converter. The measured loop gain of the system correlates very well with the modelling results. The achieved controller crossover frequency is similar to 1/10 of the switching frequency which is close to the crossover frequency of analogue peak current mode controllers.

关键词： DC-DC power convertors electric current control field programmable gate arrays high-performance digital replica analogue peak current mode control DC-DC converter digital peak current mode controller inner current loop buck converter field programmable gate array power 100 W

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Predictive Motion Planning with Pipelined Feature-Based Obstacle Avoidance

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2016年第4期39卷 967-975页

作者： Seiferth, Christoph Joos, Alexander Frangenberg, Michael Fichter, Walter Univ Stuttgart Inst Flight Mech & Control D-70569 Stuttgart Germany

An efficient method for the approximate solution of a finite-horizon constrained optimal control problem was proposed that uses quantized and discretized control candidates in such a way that a real-time implementation on a small onboard computer is feasible. For obstacle or collision avoidance, an algorithm using predicted trajectory points and visible three-dimensional features in a point cloud was presented that is suitable for a parallel and pipelined implementation on a field-programmable gate array. This allows for a very large number of obstacles to be checked by using raw sensor data only without further processing. The second option of an obstacle cost function uses a barrier function approach. It is designed so that the cost tends to infinity if the distance between a predicted trajectory point and an obstacle approaches the minimum distance. Choosing this approach helps to influence the flown trajectory, even when the vehicle has a much greater distance to possible obstacles than the minimum distance, since features always introduce costs on a trajectory and not only if the predicted trajectory violates the minimum distance requirement.

关键词： Model Predictive Control Motion Planning field programmable gate array Flight Testing Optimal Control Quaternions Onboard Computing Navigation Algorithm LIDAR VTOL

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Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

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IEEE ACCESS 2016年 4卷 2005-2018页

作者： Lorandel, Jordane Prevotet, Jean-Christophe Helard, Maryline Natl Inst Appl Sci INSA IETR F-35708 Rennes France

In this paper, a new and efficient methodology is proposed to quickly and precisely evaluate the power consumption and performance of wireless communication base-band systems implemented in field-programmable gate arrays (FPGAs). As the complexity of such systems is still growing, being able to estimate both power and performance of a design has become a major issue. FPGA devices constitute a promising technology in this highly constrained context. However, to respect their power budget, designers need to explore the design space very soon in the design process. This is performed prior to any implementation. Based on the innovative definition of a scenario, which enables comparison among wireless communication applications in a formal manner, each parameter can be evaluated to meet the power-performance tradeoff. In this paper, the proposed methodology is realized in two steps using a low-level characterization process and high-level system modeling. Another major contribution consists in considering components' time activity to refine power estimations results. We demonstrate the effectiveness of the proposed methodology throughout several domain-specific use cases, with a focus on hardware base-band processing in the wireless communication domain. As compared with current low-level FPGAs vendor tools, an important speedup factor is obtained, and a maximal relative error lower than 5% is reached.

关键词： Wireless communication field programmable gate array power consumption system modelling SystemC

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