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Embedding an Electrical System Real-Time Simulator with Floating-Point Arithmetic in a field programmable gate array

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ENERGIES 2021年第24期14卷 8404页

作者： Queiroz, Janailson Carvalho, Sarah Barros, Camila Barros, Luciano Barbosa, Daniel Univ Fed Rio Grande do Norte Elect & Comp Engn Grad Program BR-59078970 Natal RN Brazil Univ Fed Paraiba Comp Syst Dept BR-58055000 Joao Pessoa Paraiba Brazil Univ Fed Bahia Elect & Comp Engn Dept BR-40170115 Salvador BA Brazil

Real-Time Digital Simulation (RTDS) is a powerful tool in modeling and analyzing electrical and drive systems because it provides an efficient and accurate process. There are several hardware devices for this type of simulation;however, their high costs have led to the increasing use of more affordable and reconfigurable technologies. In this context, many logic blocks and storage elements make the field programmable gate array (FPGA) an ideal device to perform RTDS. This work proposes a technique to embed a real-time digital simulator in an FPGA through Hardware Description Language (HDL) since it provides liberty in the architecture choice and no dependency on commercial ready-made hardware-software packages. The approach proposed focuses on system design developing with expression tree graph, synthesizing and verifying, prioritizing the performance and design accuracy concerning area and power consumption. Thus, the result acquisition occurs at a time step considered in real-time. A simulation of a direct current (DC) motor speed control has been incorporated into this work as an example of application, which includes the embedding and simulation of the electric machine and its drive system. Performance tests have shown that the developed simulator is real-time and makes possible realistic analysis of the interaction between the plant and its control. In addition, an idea of the hardware requirement for real-time simulation is proposed based on the number of mathematical operations.

关键词： real-time simulation field programmable gate array reconfigurable computing dynamic systems hardware description language

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Experimental verification of the effectiveness of a new circuit to mitigate single event upsets in a Xilinx Artix-7 field programmable gate array

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103327-103327页

作者： Smith, Farouk Omolo, Joshua Nelson Mandela Univ Port Elizabeth South Africa

A single event transient (SET) filtering technique for the Xilinx Artix-7 field programmable gate array (FPGA) is investigated experimentally. The technique combines AND - OR gate circuits to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. It uses fewer resources than the widely used Triple Modular Redundancy (TMR) and significantly reduces event upsets in a FPGA. This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations, by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

关键词： field programmable gate array Application specific integrated circuits Single event upsets Triple modular redundancy Device under test

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Implementation of encoder and decoder for low-density parity-check codes in continuous-variable quantum key distribution on a field programmable gate array

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OPTICAL ENGINEERING 2023年第1期62卷 014105-014105页

作者： Sun, Xiunan Liang, Hao Univ Sci & Technol China Sch Cybersci Hefei Peoples R China Univ Sci & Technol China State Key Lab Particle Detect & Elect Hefei Peoples R China Univ Sci & Technol China Dept Modern Phys Hefei Peoples R China

Quantum key distribution (QKD) can provide an unconditionally secure communication encryption method. Continuous-variable QKD (CVQKD) requires extracting the key from the noisy channel, leading to higher requirements for the error-correcting codes used in multidimensional reconciliation. We extend the quasi-cyclic low-density parity-check of the radio design for the global 5G mobile communication technology standard to achieve error correction under lower signal-to-noise ratio on integrated hardware. A field programmable gate array (FPGA) chip is used to realize the approximate lower triangular matrix encoding algorithm, and the core module only has the circular shift register, which reduces the encoding complexity, improves the encoding efficiency, and reduces the hardware resource consumption. For extended super-long code words, the decoding algorithm requires additional hardware resources to implement, which the previous algorithm cannot meet. Therefore, we present a hardware implementation of offset minimum sum algorithm (OMSA), which can avoid operations of complex mathematical formula. The offset factor of OMSA reduce the error caused by the low accuracy of calculation on the hardware. The update of the decoding information is layered in a partially parallel way in the matrix to achieve the cross processing of node information. It speeds up the transmission of information between different nodes and the convergence of decoding algorithm of low-complexity parallel structure. Simulation results show that the maximum theoretical coordination efficiency is 85% when the code with block length is 69632 at a bit rate of 22/68 and the signal-to-noise ratio asymptotic threshold is 0.7. Using an FPGA, similar to 0.1 frame error rate was achieved, but with a zero-bit error rate, the optimal achievable secret key rate is about 200 Kbps at 30-km distance theoretically. For a 200-MHz system clock on the successfully decoded block, 125 Gbps encoding throughput and 472 Kbps d

关键词： continuous-variable quantum key distribution quasi-cyclic low-density parity-check offset minimum sum algorithm field programmable gate array

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A reconfigurable smart interface based on IEEE 1451 and field programmable gate array for multiple Internet of Things devices

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INTERNATIONAL JOURNAL OF DISTRIBUTED SENSOR NETWORKS 2017年第2期13卷 1-1页

作者： Wang, Shulong Hou, Yibin Gao, Fang Ji, Xinrong Beijing Univ Technol Beijing Adv Innovat Ctr Future Internet Technol Beijing 100124 Peoples R China Beijing Univ Technol Beijing Engn Res Ctr IoT Software & Syst Beijing Peoples R China

The Internet of Things is becoming increasingly important in traffic, medical treatment, and other industry fields. With the development of the Internet of Things technology, lots of new "things'' need to be accessed to the Internet of Things. Currently, Internet of Things applications adopt multiple methods to access the heterogeneous devices. How to provide unified access means for those "things'' is a fundamental issue. To solve this problem, a new method is proposed in this article to design a reconfigurable smart interface for multiple Internet of Things devices. The IEEE 1451 standard is adopted for this design, and it comprehensively specifies the smart transducer design and relevant interface protocol to implement the intelligent acquisition for common sensors and actuators. field programmable gate array is adopted for the implementation of this design to reduce consumption of resources and enable the reconfiguration of the whole system. Performance of the proposed system is evaluated, and good performance is achieved in practical application for office environment monitoring.

关键词： Internet of Things IEEE 1451 field programmable gate array sensor actuator

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Real-time hybrid simulation based on vector form intrinsic finite element and field programmable gate array

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STRUCTURAL CONTROL & HEALTH MONITORING 2019年第1期26卷 e2277-e2277页

作者： Duan, Yuanfeng Tao, Junjie Zhang, Hongmei Wang, Sumei Yun, Chungbang Zhejiang Univ Coll Civil Engn & Architecture Hangzhou Zhejiang Peoples R China Tongji Univ State Key Lab Disaster Reduct Civil Engn Shanghai 20092 Peoples R China

The numerical substructure of a real-time hybrid simulation (RTHS) has been considerably simplified through condensation methods to relieve the burden incurred by computation. However, this simplification severely limits the application of RTHS to structures whose numerical parts are complex and require a large number of degrees of freedom (DOFs) to model. Thus, in this study, a vector form intrinsic finite element (VFIFE) analysis is introduced to RTHS with numerical substructures containing a large number of DOFs. A field programmable gate array (FPGA) is also employed to speed-up the numerical simulation of the VFIFE through parallel computing in RTHS. The characteristics of this parallel RTHS platform using VFIFE and FPGA are discussed in detail in this paper. A simple RTHS was carried out to verify the feasibility of this new platform, followed by a complex virtual RTHS to show its powerful computational capability.

关键词： degree of freedom field programmable gate array parallel computing real-time hybrid simulation vector form intrinsic finite element

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A low-jitter timing generator based on completely on-chip self-measurement and calibration in a field programmable gate array

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REVIEW OF SCIENTIFIC INSTRUMENTS 2021年第11期92卷 114703-114703页

作者： Qiu, Wenjie Xie, Jianfeng Liu, Qinying Han, Xiaotao Huazhong Univ Sci & Technol Wuhan Natl High Magnet Field Ctr Wuhan 430074 Peoples R China Huazhong Univ Sci & Technol State Key Lab Adv Electromagnet Engn & Technol Wuhan 430074 Peoples R China

This paper presents a high-stability and low-jitter Arbitrary Timing Generator (ATG) design based on the Xilinx field programmable gate array (FPGA) and its special integrated delay line. In recent years, FPGA-based or application specific integrated circuit-based delay lines have been used to achieve picosecond-level timing resolution. Devices with pure digital delay methods can only acquire triggers at the clock rising edges when triggered externally. Therefore, there is a large time irregularity caused by the uncertainty of the entry time of the trigger, which is difficult to compensate and leads to a large time jitter of outputs. We describe the design of an ATG that includes jitter self-measurement and calibration methods, which is available for both internal and external trigger modes. This structure is completely based on the FPGA's own resources and has the advantages of being simple and flexible. Experimental results show a sub-nanosecond timing resolution of 78 +/- 20 ps with a minimum of 120 ps and a time jitter of 160 +/- 20 ps in the external trigger mode after compensation.

关键词： Topics Phase lock loop field programmable gate array Digital-to-analog converter Analog-to-digital converter Diseases and conditions Energy use and applications Printed circuit board Delay lines Application specific integrated circuit Oscilloscopes

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A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array

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Journal of Chongqing University 2008年第3期7卷 228-233页

作者：陈永军 College of Electrical and Electronic Engineering Huazhong University of Science and Technology College of Electronics and Information Yangtze University

A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.

关键词： fuzzy control direct torque control field programmable gate array permanent magnet synchronous motor

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Vector control implementation in field programmable gate array for 200 kHz GaN-based motor drive systems

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JOURNAL OF ENGINEERING-JOE 2018年第13期2018卷 650-653页

作者： Luo, Zhiwen Li, Yongdong Zhang, Xinyan Wang, Kui Xinjiang Univ Coll Elect Engn Urumqi Peoples R China Tsinghua Univ Dept Elect Engn Beijing Peoples R China

GaN devices used to drive a three-phase inverter drive motor can greatly improve the switching frequency and increase the power density. However, the traditional microcontroller unit (MCU) controller cannot achieve high switching frequency single-cycle control. This paper describes the use of GaN devices in the design of a three-phase motor drive system to drive a permanent magnet synchronous motor and vector control algorithm, that is completely implemented in a field programmable gate array. The system achieves 200-kHz switching frequency single-cycle precise control, as verified by the experimental results.

关键词： machine vector control permanent magnet motors gallium compounds field programmable gate arrays III-V semiconductors wide band gap semiconductors microcontrollers frequency control synchronous motor drives field programmable gate array permanent magnet synchronous motor vector control algorithm switching frequency single-cycle precise control MCU controller three-phase inverter drive motor system frequency 200 0 kHz GaN

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Realization of a sensorless speed controller for permanent magnet synchronous motor drives based on field programmable gate array technology

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ADVANCES IN MECHANICAL ENGINEERING 2017年第11期9卷

作者： Risfendra Kung, Ying-Shieh Wang, Ming-Shyan Huang, Liang-Chiao Southern Taiwan Univ Sci & Technol Dept Elect Engn 1 Nan Tai St Tainan 710 Taiwan Univ Negeri Padang Dept Elect Engn Padang Indonesia Ind Technol Res Inst Green Energy & Environm Res Labs Hsinchu Taiwan

This article presents a hybrid sensorless speed controller for permanent magnet synchronous motor drives using field programmable gate array technology. The I-f startup strategy is applied to permanent magnet synchronous motor drives at the startup condition and then it will smoothly switch to extended Kalman filter-based sensorless field-oriented control at the adequate condition. The I-f startup is a simple strategy and suitable for the low-speed sensorless control without initial rotor position estimation and machine parameters estimation. Meanwhile, the extended Kalman filter-based sensorless field-oriented control is appropriate for the medium- and high-speed sensorless control. Therefore, combining two approaches, the sensorless permanent magnet synchronous motor can be smoothly operated from a standstill to a high-speed condition. In this article, first, the mathematical modeling of permanent magnet synchronous motor is introduced. Also, the I-f startup strategy is conducted, and the rotor position estimation algorithm by extended Kalman filter is derived. Second, a very high-speed integrated circuit hardware description language is presented to describe the behavior of the adopted estimation and control algorithm. This application codes have been confirmed using Simulink and ModelSim co-simulation. Finally, a field programmable gate array-based experimental system is utilized to verify the correctness and effectiveness of the proposed hybrid sensorless speed controller for a permanent magnet synchronous motor and a ceiling fan motor.

关键词： Sensorless controller permanent magnet synchronous motor I-f startup extended Kalman filter field programmable gate array Simulink/ModelSim co-simulation ceiling fan motor

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Design and Implementation of field programmable gate array Based Baseband Processor for Passive Radio Frequency Identification Tag

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INTERNATIONAL JOURNAL OF ENGINEERING 2017年第1期30卷 127-133页

作者： Dyamannavr, N. M. Kurahatti, N. G. Christina, A. Govt Engn Coll Engn Kushalnagar Kushalnagar Karnataka India East Point Coll Engn & Technol Bangalore Karnataka India

In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix Code (DMC) technique is used. The digital base band processor has been simulated and implemented using Xilinx platform. The complete design is verified and tested on Spartan-6 field programmable gate array (FPGA) board. The performance of system is measured in terms of power. The synthesis result shows that, the power required for complete design of digital baseband processor is 5mW on a supply voltage of 1.2 V.

关键词： Radio Frequency Identification Base Band Processor Hardware Descriptive Language field programmable gate array

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