检索结果-内蒙古大学图书馆

Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory

COMPUTING IN SCIENCE & ENGINEERING 2016年第1期18卷 80-87页

作者： Arcas-Abella, Oriol Armejach, Adria Hayes, Timothy Malazgirt, Gorker Alp Palomar, Oscar Salami, Behzad Sonmez, Nehir Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Comp Architecture E-08028 Barcelona Spain Barcelona Supercomp Ctr Comp Architecture Barcelona Spain Bogazici Univ Comp Engn Istanbul Turkey Barcelona Supercomp Ctr Parallel Paradigms Grp Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain Barcelona Supercomp Ctr Parallel Paradigms Res Grp Barcelona Spain

Database management systems have become an indispensable tool for industry, government, and academia, and form a significant component of modern datacenters. They can be used in a multitude of scenarios, including online analytical processing, data mining, e-commerce, and scientific analysis. Given the exponential growth in new data produced each year, there is a pressure on software and hardware developers to create datacenters that can cope with increasing requirements. The authors look at the organization of a modern relational database management system and propose optimizations and redesign for the storage access, memory, and CPU.

关键词： computer centres field programmable gate arrays microprocessor chips query processing relational databases CPU FPGA data center field programmable gate array hardware acceleration query processing relational database management system Computer architecture Database management field programmable gate arrays Memory management Query processing Random access memory Software development computer architecture database management system hardware scientific computing supercomputing

来源：评论

学校读者我要写书评

暂无评论

Implementation of Shunt Active Filter for Harmonic Compensation in a 3 Phase 3 Wire Distribution Network

引用

Energy Procedia 2017年 117卷 172-179页

作者： V.K. Arun Shankar N. Senthil Kumar Research Scholar School of Electrical Engineering VIT University Vellore 632014 India Associate Professor School of Electrical Engineering VIT University Chennai Campus India

This paper explores the modeling of a Proportional Integral (PI) and fuzzy logic controller (FLC) based, shunt active power filter (SAPF) for a three wire network to compensate current harmonics fed to a nonlinear load. In the fuzzy logic controlled SAPF mathematical model of the system is not required since it is based on an inference system incorporating intelligence derived through human expertise. The PI controlled and fuzzy logic based (SAPF) have been developed using the Simulink tool box of MATLAB. Simulation results illustrate that the fuzzy logic based active filter outperforms the PI based shunt active filter. To validate the simulation results a hardware setup is developed making using of the instantaneous Id-Iq theory using for a three phase three wire system. The hardware results were found to match closely with simulation outputs.

关键词： Shunt active filter PQ Theory dq Theory field programmable gate array Total harmonic distortion(THD)

来源：评论

学校读者我要写书评

暂无评论

Multiple perspectives on the hardware implementations of biological neuron models and programmable design aspects

引用

TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第3期24卷 1729-1746页

作者： Korkmaz, Nimet Ozturk, Ismail Kilic, Recai Erciyes Univ Fac Engn Dept Elect & Elect Engn Kayseri Turkey

A few individual design examples of programmable device-based biological neuron model implementations are available in the literature, but there is no comprehensive study that examines analog and digital programmable design examples of frequently studied biological neuron model implementations. The aim of this paper is to present a comparative study about programmable and reconfigurable implementations of the FitzHugh-Nagumo, Izhikevich, and Hindmarsh-Rose neuron models. Since field programmable analog array (FPAA) and field programmable gate array (FPGA) devices offer several advantages such as flexible design possibilities, reduction of the complexity of design, real-time modification, and software control for programmable and reconfigurable implementations of neuron models and neural structures, they are preferred in these implementations as analog and digital programmable devices. Experimental results agree with the numerical simulations and verify the design effectiveness of FPAA- and FPGA-based implementations.

关键词： Neuron models field programmable analog array field programmable gate array circuit implementation

来源：评论

学校读者我要写书评

暂无评论

Hardware Implementation of Reconfigurable 1D Convolution

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2016年第1期82卷 1-16页

作者： Rao, Lei Zhang, Bin Zhao, Jizhong Xi An Jiao Tong Univ Xian 710049 Shaanxi Peoples R China

Convolution has been extensively used in image processing and computer vision, including image enhancement, smoothing, and structure extraction. However, convolution operation typically requires a significant amount of computing resources. A novel one-dimensional (1D) convolution processor with reconfigurable architecture is implemented in this study. This processor is a combination of a line buffer, controller units, as well as a reconfigurable and separable convolution module. The use of a reconfigurable architecture and separable convolution approach improves the flexibility and performance of the convolution processor. The reconfigurable and separable convolution array, which is the main component of the processor, can simultaneously execute convolution operation with different kernels, with a maximum kernel size of up to 24 x 24. Experimental results show that the maximum frames rate of the processor is approximately 194 frames per second (fps), which exceeds the real-time requirement. Synthesis results show that the processor occupies 13.39 mm (2) at a 204 MHz system clock and consumes a power of 419 mW at maximum kernel size at a 120 MHz system clock in SMIC 0.18 mu m CMOS technology. Verification experiments on field programmable gate arrays (FPGAs) demonstrate that the processor is suitable for real-time image processing applications even for high-resolution images.

关键词： Convolution field programmable gate array Reconfigurable architecture

来源：评论

学校读者我要写书评

暂无评论

Real-time simulation of modular multilevel converters for controller hardware-in-the-loop testing

引用

IET POWER ELECTRONICS 2016年第1期9卷 42-50页

作者： Matar, Mahmoud Paradis, Dominic Iravani, Reza Univ Toronto Ctr Appl Power Elect Toronto ON Canada Ain Shams Univ Elect Power & Machines Dept Cairo Egypt Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

This study presents a field programmable gate array (FPGA)-based real-time simulation platform for realistic-size modular multilevel converters (MMCs). This development is primarily intended for controller hardware-in-the-loop (HIL) testing for MMC-based high-voltage direct current (HVDC) transmission systems. Although the real-time simulation of MMC-based systems is particularly challenging due to the presence of thousands of power electronic switches, yet, it is still possible based on adopting a computationally efficient MMC model and the use of a high-performance parallel computational engine. This study focuses on the design and implementation of the parallel computational engine that solves the mathematical model of an enhanced computationally efficient MMC model on the FPGA platform. Moreover, provided are the implementation results and their verifications corresponding to the real-time simulation of a 401-level MMC and the HIL testing of the controllers of the 401-level MMC-HVDC link between France and Spain.

关键词： field programmable gate arrays HVDC power transmission power convertors real-time simulation modular multilevel converters controller hardware-in-the-loop testing field programmable gate array FPGA-based real-time simulation platform realistic-size modular multilevel converters HIL testing MMC-based high-voltage direct current transmission systems HVDC transmission systems power electronic switches parallel computational engine

来源：评论

学校读者我要写书评

暂无评论

FPGA-Based Web Services - Infinite Potential or a Road to Nowhere?

引用

IEEE INTERNET COMPUTING 2016年第1期20卷 44-51页

作者： Brzoza-Woch, Robert Nawrocki, Piotr AGH Univ Sci & Technol Dept Comp Sci PL-30059 Krakow Poland

field-programmable gate array (FPGA) technology could have significant potential in the construction of Web services, but it generates multiple issues that software and hardware designers must overcome first. As a Web service hardware platform, the FPGA could be an experimental yet interesting and powerful alternative to standard solutions based on microprocessors and microcontrollers. Here, the authors share their thoughts about the possibility of using FPGA chips to implement environment-aware embedded Web services.

关键词： field programmable gate arrays Internet Web Services Economics Distributed Processing Ubiquitous Computing Internet Of Things Ubiquitous Computing Internet Web Technologies Io T Internet Of Things FPGA field programmable gate array Web Services Distributed Systems Data Path Design

来源：评论

学校读者我要写书评

暂无评论

Performance analysis of free space optical communication in open-atmospheric turbulence conditions with beam wandering compensation control

引用

IET COMMUNICATIONS 2016年第9期10卷 1096-1103页

作者： Anthonisamy, Arockia Bazil Raj Durairaj, Padmavathi Paul, Lancelot James Def Inst Adv Technol Elect Engn Pune Maharashtra India Thiagarajar Coll Engn Comp Sci & Engn Madurai Tamil Nadu India Indian Inst Astrophys Opt Div Bangalore Karnataka India

Among various atmospheric effects, beam wandering is the main cause for the major power loss in free space optical communication (FSOC) which cannot be resolved without incorporating the beam wandering compensation (BWC) control. To prove this prerequisite, a 155 Mbps data transmission experimental setup is built with necessary optoelectronic components for the link range of 0.5 km at an altitude of 15.25 m. A neuro-controller is developed inside the field programmable gate array and used to stabilise the received beam at the centre of the detector plane so as to perfectly couple the power in the bucket to the optical detector. The Q-factor and bit error rate variation profiles are calculated using the signal statistics obtained from the eye-diagram. The performance improvements on the FSOC system due to the incorporation of BWC control are investigated and discussed in terms of various communication quality assessment key parameters.

关键词： free-space optical communication optoelectronic devices field programmable gate arrays neurocontrollers beam steering compensation Q-factor error statistics atmospheric turbulence telecommunication computing performance analysis free space optical communication FSOC system open-atmospheric turbulence conditions beam wandering compensation control atmospheric effects power loss optoelectronic components neurocontroller field programmable gate array optical detector Q-factor bit error rate variation profiles signal statistics altitude 15 25 m bit rate 155 Mbit s

来源：评论

学校读者我要写书评

暂无评论

BFT: a placement algorithm for non-rectangle task model in reconfigurable computing system

引用

IET COMPUTERS AND DIGITAL TECHNIQUES 2016年第3期10卷 128-137页

作者： Wang, Chaohui Wu, Weiguo Nie, Shiqiang Qian, Depei Xi An Jiao Tong Univ Dept Comp Sci & Technol Xian Shaanxi Peoples R China Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China

Task scheduling and placement problem is one of the most significant and time-consuming parts in reconfigurable computing (RC) system. Many investigators have explored on the subject, and most of the traditional studies are concentrated on the rectangle task model, which is inconsistent with objective task shape placed in a field programmable gate array (FPGA) but simplifies the system complexity. Rectangle task model produces inner fragments which reduces utilisation of reconfigurable resources in an FPGA. In this study, a task model transformation strategy and an innovative best-fit transformation (BFT) placement algorithm are proposed for a non-rectangle task model to improve the performance of an RC system in rejection rate and total execution time. According to simulation experiments, BFT algorithm reduced the rejection rate by 15% and 7% compared with that of the first-fit algorithm and the best-fit algorithm, respectively. Multi-shape placement algorithm and 3D compaction algorithm are also cited to compare with the BFT algorithm. The result shows that the BFT algorithm has less total execution time in short laxity period and lower rejection rate in large laxity period. Compared with 3D compaction algorithm, the proposed algorithm reduced the total execution time up to 10.79%.

关键词： reconfigurable architectures field programmable gate arrays processor scheduling BFT nonrectangle task model reconfigurable computing system task scheduling and placement problem RC system field programmable gate array FPGA system complexity reconfigurable resources task model transformation strategy innovative best-fit transformation placement algorithm total execution time rejection rate first-fit algorithm multishape placement algorithm 3D compaction algorithm

来源：评论

学校读者我要写书评

暂无评论

Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots

引用

TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第6期24卷 5055-5067页

作者： Tuncer, Adem Yildirim, Mehmet Yalova Univ Fac Engn Dept Comp Engn Yalova Turkey Kocaeli Univ Fac Engn Dept Informat Syst Engn Kocaeli Turkey

This paper presents a hardware realization of a genetic algorithm (GA) for the path planning problem of mobile robots on a field programmable gate array (FPGA). A customized GA intellectual property (IP) core was designed and implemented on an FPGA. A Xilinx xupv5-1x110t FPGA device was used as the hardware platform. The proposed GA IP core was applied to a Pioneer 3-DX mobile robot to confirm its path planning performance. For localization tasks, a camera mounted on the ceiling of the laboratory was utilized to receive images and allow the robot to determine its own location and the obstacles in the environment. In this way, procedures of path planning were tested in a real laboratory environment. An impressive time speedup was achieved when compared with its software implementation. Experimental results illustrate the effectiveness of the GA IP core hardware.

关键词： Genetic algorithm path planning mobile robot field programmable gate array intellectual property core

来源：评论

学校读者我要写书评

暂无评论

Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm

引用

IET CIRCUITS DEVICES & SYSTEMS 2016年第4期10卷 309-316页

作者： Puthenpurayil, Shiju Padmanabhan Chakrabarti, Indrajit Virdi, Rishi Kaushik, Harsh Indian Inst Technol Elect & Elect Commun Engn Dept Kharagpur 721302 W Bengal India

This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (ARPS) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of ARPS algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 mu m) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm(2). A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 x 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 x 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 x 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.

关键词： motion estimation image matching video coding search problems VLSI field programmable gate arrays application specific integrated circuits very large scale integration architecture adaptive rood pattern search algorithm block-matching motion estimation video encoder ARPS algorithm field programmable gate array application specific integrated circuit ASIC peak signal-to-noise ratio Virtex-4 FPGA Xilinx 14 2 Synopsys design vision tool size 0 18 mum frequency 100 MHz power 4 54 mW

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：