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Rebuttal to "Comments on 'A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing'"

IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2016年第11期11卷 2626-2627页

作者： Zhang, Jiliang Qu, Gang Northeastern Univ Software Coll Shenyang 110169 Peoples R China Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

Concerns have been raised about our recently published article on a PUF-FSM binding scheme for FPGA IP protection and Pay-per-Device licensing. In a comment, the authors first analyzed the simple 4-bit license example we used in the article and claimed that the low overhead configuration of the FSM binding does not provide sufficiently high level of security. Then they analyzed the FSM binding structure and claimed that when a 128-bit long license is used to provide high security, the PUF-FSM scheme will incur unacceptable overhead. Both the analyses seem correct. However, they focus on some illustrative examples of our proposed binding scheme, not the main contribution which is a non-encryption based binding mechanism and its application to FPGA IP protection and pay-per-device licensing. The first claim on the low security of the 4-bit license example is true, but it is just a simple example, in reality, the key/license will be much longer. For the second claim, the balance of overhead and security can be addressed by some simple tricks such as adding few black holes used in FSM binding and the augment of number of inputs of STG. In this rebuttal, we will elaborate these.

关键词： field programmable gate array IP protection IC metering pay-per-device licensing hardware security binding

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Ripple-reduced model predictive direct power control for active front-end power converters with extended switching vectors and time-optimised control

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IET POWER ELECTRONICS 2016年第9期9卷 1914-1923页

作者： Fang, Hui Zhang, Zhenbin Feng, Xiaoyun Kennel, Ralph Southwest Jiaotong Univ Sch Elect Engn Chengdu Sichuan Peoples R China Tech Univ Munich Sch Elect Engn & Informat Munich Germany

Model predictive control (MPC) is an attractive technique for power electronics and drives. It requires no extra modulators and considers the non-linear nature of the power converter, so remarkable control performance can be achieved. However, since the conventional MPC scheme uses only one switching state during the whole control interval, ripples of the control variables are more evident than that of the classical modulator based techniques. This study proposed a ripple-reduced model predictive direct power control (RR-MPDPC) scheme for the grid-tied active front end using a fully field programmable gate array-based platform. The novelty of the proposed RR-MPDPC is that through extended switching vectors and time-optimised control, more freedoms and precise tracking possibility are realised in the predictive controller. The proposed control scheme is compared with the conventional MPDPC and the recently reported duty optimal MPDPC scheme (DutyOpt-MPDPC) through experimental data. Experimental results confirm that better performance is achieved using the proposed RR-MPDPC scheme.

关键词： predictive control power control power convertors power electronics electric drives field programmable gate arrays optimal control modulators ripple-reduced model predictive direct power control RR-MPDPC active front-end power converters extended switching vectors time-optimised control power electronics power drives switching state control variables classical modulator grid-tied active front end field programmable gate array predictive controller duty optimal MPDPC scheme DutyOpt-MPDPC

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Predictive current control of distribution static compensator for load compensation in distribution system

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IET GENERATION TRANSMISSION & DISTRIBUTION 2016年第10期10卷 2410-2423页

作者： Venkatraman, Kandadai Selvan, Manickavasagam Parvathy Moorthi, Sridharan Natl Inst Technol Dept Elect & Elect Engn Power Converters Res Lab Tiruchirappalli 620015 Tamil Nadu India Natl Inst Technol Dept Elect & Elect Engn VLSI Syst Res Lab Tiruchirappalli 620015 Tamil Nadu India

Predictive control is an emerging alternative in the control of power converters because of its potential for achieving fast transient response and increased control accuracy. Research on this topic has increased in recent years owing to the availability of high speed digital controllers that can be used for the control of power electronic systems. This study proposes a predictive current control scheme for an improved topology of distribution static compensator (DSTATCOM) intended for load compensation. The proposed strategy derives the converter switching pulses using a cost function that defines the desired system behaviour. An improved DSTATCOM topology employing predictive current control algorithm tracks reference current effectively and makes source current sinusoidal and also in-phase with voltage at the point of common coupling in both steady state and transient conditions. In addition, this scheme does not require any modulation technique. The control scheme has been implemented using field programmable gate array. Simulation and experimentation have been carried out to verify and validate the performance of the proposed scheme and the results are reported in this study.

关键词： predictive control electric current control power distribution control static VAr compensators power convertors field programmable gate arrays predictive current control distribution static compensator load compensation distribution system DSTATCOM converter switching pulses point of common coupling field programmable gate array

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Modeling and Experimental Study on the Dynamic Stiffness of an Electromechanical Actuator

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JOURNAL OF SPACECRAFT AND ROCKETS 2016年第4期53卷 708-719页

作者： Kim, Sang Hwa Tahk, Min-Jea Korea Adv Inst Sci & Technol Dept Aerosp Engn 335 Gwahangno Daejeon 305701 South Korea Agcy Def Dev Daejeon 305600 South Korea

An increasing number of applications of the electromechanical actuator in the control actuation system of flight vehicles have recently required an accurate electromechanical actuator model. In this study, the modeling method of the dynamic stiffness of the electromechanical actuator, including nonlinear parameter estimation, is presented. The validation of a dynamic stiffness model is executed through comparison of experimental and simulation results, indicating good consistency of experimental data with the simulation results. Additionally, in order to analyze the effects of nonlinear parameters of the electromechanical actuator on the dynamic stiffness, pragmatic experimental approaches are explained and performed using the electromechanical actuator hardware and a hydraulic excitation system that is used for inputting an aerodynamic load into the electromechanical actuator. Experimental and simulation results showed that the dynamic stiffness changed, depending on the magnitude of the external load and the preload. The dynamic stiffness of the electromechanical actuator also increased under conditions of small free play and large static stiffness values of the electromechanical actuator components.

关键词： Electromechanical Actuator Stiffness Aerodynamic Properties Flight Vehicle Damping Coefficient Torque Sensors Data Acquisition Potentiometer field programmable gate array Power Supplies

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Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays

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IET SIGNAL PROCESSING 2015年第5期9卷 449-456页

作者： Vandenbussche, Jean-Jacques Lee, Peter Peuteman, Joan Katholieke Univ Leuven KU Leuven Kulab Dept ESAT Fac Engn Technol Louvain Belgium Univ Kent Sch Engn & Digital Arts Canterbury CT2 7NT Kent England

This paper describes how modern field programmable gate array (FPGA) technology can be used to build practical and efficient multiplicative finite impulse response (MFIR) filters with low-pass, high-pass, band-pass and band-stop characteristics. This paper explains how MFIR structures can be built with or without linear phase characteristics and implemented efficiently on modern FPGA architectures using fixed-point arithmetic without incurring stability problems or limit cycles which commonly occur when using equivalent infinite impulse response structures. These properties have a particular importance for applications such as tunable resonators, narrow band rejectors and linear phase filters which have demanding, narrow transition band requirements. The results presented in this paper indicate that MFIR filters are, for some applications, a viable alternative to existing filter structures when implemented on an FPGA.

关键词： field programmable gate arrays FIR filters low-pass filters high-pass filters band-pass filters band-stop filters linear phase filters IIR filters multiplicative finite impulse response filter MFIR filter field programmable gate array low-pass characteristics band-stop characteristics high-pass characteristics band-pass characteristics linear phase characteristics modern FPGA architecture fixed-point arithmetic equivalent infinite impulse response structures

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Towards realisation of wireless sensor network-based water pipeline monitoring systems: a comprehensive review of techniques and platforms

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2016年第5期10卷 420-426页

作者： Obeid, Abdulfattah M. Karray, Fatma Jmal, Mohamed Wassim Abid, Mohamed Qasim, Syed Manzoor BenSaleh, Mohammed S. King Abdulaziz City Sci & Technol Natl Ctr Elect & Photon Technol Riyadh Saudi Arabia Natl Engn Sch Sfax Comp & Embedded Syst Lab Sfax Tunisia Res Ctr Informat Multimedia & Digital Data Proc C Technopk Sfax Tunisia

Huge quantities of water are wasted on a daily basis worldwide because of leakages in water-transporting infrastructures causing water shortage, injuries, and so on. This problem is typically worsened by the lack of advanced monitoring systems. In this respect, wireless sensor networks (WSNs) have revolutionised water-monitoring systems providing reliable inspection, feasible communication and performing applications. This study presents a comprehensive survey on software and hardware solutions proposed in the literature for water pipeline infrastructure monitoring. In fact, several leak detection and localisation techniques like acoustic, ultrasound or pressure ones are studied and evaluated. Several research works tried to implement these techniques using different types of WSN platforms including microcontroller, digital signal processor, application-specific integrated circuit and field programmable gate array. These platforms are reviewed and discussed while highlighting their advantages and drawbacks. Finally, an integrated energy-aware system-on-chip solution using high-performance hardware is proposed to achieve optimal and reliable results.

关键词： wireless sensor networks pipelines microcontrollers digital signal processing chips application specific integrated circuits field programmable gate arrays wireless sensor networks water pipeline infrastructure monitoring microcontroller digital signal processor application-specific integrated circuit field programmable gate array integrated energy-aware system-on-chip solution high-performance hardware

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Real-time digital multi-function protection system on reconfigurable hardware

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IET GENERATION TRANSMISSION & DISTRIBUTION 2016年第10期10卷 2295-2305页

作者： Wang, Yifan Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

This study proposes a multi-function power system protective relay hardware design built with various functional hardware processing cores on the field programmable gate array (FPGA). This practical and systematic method lends itself to a paralleled and pipelined hardware emulation of individual signal processing and protection components. Detailed emulation designs are presented for the following protective relays: distance, directional overcurrent, voltage, and frequency protection. The necessary signal processing functions required to operate these relays are also emulated, allowing the protection system to be stand-alone and fed with instantaneous fault data. Real-time experimental results are presented to verify the functions of the target hardware relay on the Xilinx((R)) Virtex-7 FPGA. Case studies provide the efficacy of the multi-function relay design in terms of accuracy, latency, and resource consumption.

关键词： relay protection power system protection field programmable gate arrays signal processing overcurrent protection power system faults real-time digital multifunction protection system multifunction power system protective relay hardware design functional hardware processing core field programmable gate array paralleled hardware emulation pipelined hardware emulation distance relay protection directional overcurrent relay protection voltage relay protection frequency relay protection signal processing function Xilinx Virtex-7 FPGA resource consumption

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A Survey of FPGA-Based LDPC Decoders

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IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 2016年第2期18卷 1098-1122页

作者： Hailes, Peter Xu, Lei Maunder, Robert G. Al-Hashimi, Bashir M. Hanzo, Lajos Univ Southampton Sch Elect & Comp Sci Southampton SO17 1BJ Hants England

Low-density parity check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed, and the parallelism of field-programmable gate array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their in-system programmability makes them far more cost-effective than application-specific integrated circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance tradeoffs are characterized, discussed, and illustrated. Seven key performance characteristics are described, namely, their processing throughput, processing latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency, and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoders.

关键词： Digital communication error correction codes low-density parity check (LDPC) codes field programmable gate array iterative decoding

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Evolutionary circuit design for fast FPGA-based classification of network application protocols

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APPLIED SOFT COMPUTING 2016年 38卷 933-941页

作者： Grochol, D. Sekanina, L. Zadnik, M. Korenek, J. Kosar, V. Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat Brno 61266 Czech Republic

The evolutionary design can produce fast and efficient implementations of digital circuits. It is shown in this paper how evolved circuits, optimized for the latency and area, can increase the throughput of a manually designed classifier of application protocols. The classifier is intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array (FPGA). The classification is performed using the first packet carrying the application payload. The improvements in latency (and area) obtained by Cartesian genetic programming are validated using a professional FPGA design tool. The quality of classification is evaluated by means of real network data. All results are compared with commonly used classifiers based on regular expressions describing application protocols. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Application protocol Classifier Cartesian genetic programming field programmable gate array

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FPGA-based design and implementation of data acquisition and real-time processing for laser ultrasound propagation

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INTERNATIONAL JOURNAL OF AERONAUTICAL AND SPACE SCIENCES 2016年第4期17卷 467-475页

作者： Abbas, Syed Haider Lee, Jung-Ryul Kim, Zaeill Korea Adv Inst Sci & Technol Dept Aerosp Engn 291 Daehak Ro Daejeon 34141 South Korea Agcy Def Dev Daejeon 34186 South Korea

Ultrasonic propagation imaging (UPI) has shown great potential for detection of impairments in complex structures and can be used in wide range of non-destructive evaluation and structural health monitoring applications. The software implementation of such algorithms showed a tendency in time-consumption with increment in scan area because the processor shares its resources with a number of programs running at the same time. This issue was addressed by using field programmable gate arrays (FPGA) that is a dedicated processing solution and used for high speed signal processing algorithms. For this purpose, we need an independent and flexible block of logic which can be used with continuously evolvable hardware based on FPGA. In this paper, we developed an FPGA-based ultrasonic propagation imaging system, where FPGA functions for both data acquisition system and real-time ultrasonic signal processing. The developed UPI system using FPGA board provides better cost-effectiveness and resolution than digitizers, and much faster signal processing time than CPU which was tested using basic ultrasonic propagation algorithms such as ultrasonic wave propagation imaging and multi-directional adjacent wave subtraction. Finally, a comparison of results for processing time between a CPU-based UPI system and the novel FPGA-based system were presented to justify the objective of this research.

关键词： Laser ultrasonic propagation imaging data acquisition signal processing field programmable gate array

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