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Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs

IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS 2016年第3期2卷 174-185页

作者： Feiten, Linus Oesterle, Jonathan Martin, Tobias Sauer, Matthias Becker, Bernd Univ Freiburg Chair Comp Architecture Georges Koehler Allee 51 D-79110 Freiburg Germany

Physically unclonable functions (PUFs) are an emerging primitive in hardware security, enabling the identification of computer-chips. A promising type particularly for FPGA implementations is the Ring Oscillator (RO) PUF, where signal delays-stemming from uncontrollable variations in the manufacturing process-are used as device-specific characteristics. Based on experimental results gathered with 38 identical Altera FPGAs, we show the existence of non-device-specific i. e., systemic RO frequency biases, traced back to (1) the internal routing within the RO's look-up tables, (2) the RO locations on the FPGAs, or (3) the non-PUF payload activity. As these biases are the same for all devices, the result is poor inter-device uniqueness and unreliable signatures under changing payloads. After characterizing these biases with a newly developed set of metrics, we suggest a method to overcome them: Using only a small sample of devices, the average bias over all devices for each RO is predicted and the relative differences caused by systemic biases are nullified. We demonstrate the viability of this method by determining the sufficient random sample sizes and showing that the inter-device uniqueness is drastically increased and the PUF signatures become reliable even under changing payload activities.

关键词： Hardware security trust physically unclonable function PUF ring oscillator RO field programmable gate array FPGA altera cyclone reliability uniqueness metric

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Multiple parallel branch with folding architecture for multichannel filtered-x least mean square algorithm

Multiple parallel branch with folding architecture for multi...

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IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Dongyuan Shi Jianjun He Chuang Shi Tatsuya Murao Woon-Seng Gan Digital Signal Processing Lab School of Electrical & Electronic Engineering Nanyang Technological University Singapore

ISBN: (纸本)9781509041183

Multichannel active noise control (MCANC) systems are commonly used in acoustic noise or vibration control, such as large-dimension ventilation ducts, open windows and mechanical structures. However, its computational load far exceeds the capabilities of digital signal processors (DSPs) and microcontrollers. Even the field programmable gate array (FPGA) cannot straightforwardly cope with the exponential increase in the computation load of MCANC systems. A novel architecture, called the multiple parallel branch with folding, is proposed for the J × J × M (J reference microphones, J secondary sources and Merror microphones) MCANC implementation with the floating-point arithmetic. This architecture addresses the tradeoff between throughput and hardware resource consumption by using parallel execution and folding. The proposed architecture is validated in an experimental setup that carries out a 4 × 4 × 4 multichannel filtered-x least mean square (FxLMS) algorithm achieving the sampling rate and throughput of 24 KHz and 18.4 Mbps, respectively.

关键词： Filtered-x least mean square algorithm multichannel active noise control field programmable gate array field programmable gate arrays Active noise control Least mean square algorithm FOLDING Throughput Building construction ARCHITECTURE iodine MULTICHANNEL parallel execution Acoustic noise Microphone Device Component sampling rate

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DESIGN AND IMPLEMENTATION OF CONFIGURABLE LOGIC BLOCK OF AN FPGA USING QUANTUM DOT CELLULAR AUTOMATA 3

DESIGN AND IMPLEMENTATION OF CONFIGURABLE LOGIC BLOCK OF AN ...

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3rd International Conference on Devices, Circuits and Systems (ICDCS)

作者： Rani, D. Gracia Nirmala Mathumitha, C. Priyadharshini, R. Rajaram, S. Thiagarajar Coll Engn Dept Elect & Commun Engn Madurai 625015 Tamil Nadu India

ISBN: (纸本)9781509023097

Quantum-dot Cellular Automata (QCA) is a promising as well as an emerging technology for implementing digital systems at the Nano - scale regime. QCA technology has a unique feature, which operates at low power, high speed and density. This feature makes QCA as an alternative technology for CMOS. The present work selects the basic components of the Configurable Logic Block (CLB) of a Xilinx field programmable gate array using QCA technology. We have designed and simulated QCA based circuits such as multiplexer, Decoders, 8-Bit LUT. The proposed multiplexer based LUT have been designed and simulated using the QCA Designer software tool. The simulation results obtained from QCA Designer Tool are compared with Cadence CMOS technology. Our proposed CLB design shows an improvement of 24% fewer QCA cells, occupies 62% lesser overall area compared to previous works. The simulation result shows that the proposed QCA technology occupies smaller area and less power consumption.

关键词： QCA Configurable Logic Block field programmable gate array Multiplexer Lookup Table Memory cell

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CONTROL SYSTEM IMPLEMENTATION ON AN FPGA PLATFORM

CONTROL SYSTEM IMPLEMENTATION ON AN FPGA PLATFORM

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14th IFAC Conference on programmable Devices and Embedded Systems (PDES)

作者： Gursoy, Handan Efe, Mehmet Onder Hacettepe Univ Dept Comp Engn Autonomous Syst Lab TR-06800 Ankara Turkey Iskenderun Tech Univ Dept Comp Engn Antakya Turkey

This paper presents PID and SMC control schemes on a field programmable gate array device (FPGA) for robot manipulators. The implementation of the control systems on FPGA by using optimal hardware resources is one of the challenging research areas in control engineering. To accomplish this, MATLAB Xilinx System Generator toolbox plays an important role in control design on an FPGA device. In this paper, FPGA-based PD and SMC controllers are designed by using MATLAB Xilinx System Generator tool for the chosen robot system. The tracking performances of the presented control schemes, implemented in Matlab/Simulink and implemented on FPGA, are compared. Robustness and good trajectory performance of the system on FPGA are demonstrated. (C) 2016, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： sliding mode controller proportional-integral-derivatrile controller field programmable gate array

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A configurable test-processor for board-level testing 19

A configurable test-processor for board-level testing

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19th Euromicro Conference on Digital System Design (DSD)

作者： Escobar, J. -H. Meza Ostendorff, S. Wuttke, H. -D. Ilmenau Univ Technol Integrated Commun Syst Grp Ilmenau Germany

ISBN: (纸本)9781509028160

The ROBSY approach is able to autonomously generate highly flexible FPGA-based test instruments for structural testing of printed circuit boards (PCBs). This paper deals with the development of an essential part of ROBSY: the test-processor. It is specialized for board-level testing and includes configuration parameters for the adaptation to the specific test case. The level of adaptation is essential for ROBSY and is not presented in other test-processors found in the literature. In order to evaluate the viability of ROBSY, the ROBSY test system was used to test the interconnections to an SRAM device. The experiments demonstrate that the ROBSY approach and test-processor are suitable for board-level testing.

关键词： board-level testing configuration test-processor automatic generation field programmable gate array

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Sucker-Rod Pump Unit Electric Drive Simulator 2

Sucker-Rod Pump Unit Electric Drive Simulator

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2nd International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM)

作者： Zyuzev, A. M. Bubnov, M., V Mudrov, M., V Ural Fed Univ Dept Elect Dr & Automat Ind Plants Ekaterinburg Russia

ISBN: (纸本)9781509013227

The sucker-rod pump unit (SRPU) electric drive simulator realized on the hardware-software complex of the National Instrument Corporation is discussed. The hardware-software complex includes a field programmable gate array (FPGA) module and programming tools. The simulator consists of pump-jack, power semiconductor converter and induction motor models operating in the real time scale. A SRPU control station can receives from the simulator such data as motor current, dynamometer card, wattmeter card, rotation speed, swing frequency, daily oil productivity of well and so on. That is why the simulator may be used for adjustment and diagnostics of SRPU control stations. Benefits of such approach are examination and adjustment of the control station conducting outside the oilfield or without stopping a pumping process.

关键词： sucker-rod pump unit field programmable gate array simulator control station pumpjack induction motor model

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Digitally Assisted Analog Predistortion Technique for Power Amplifier 88

Digitally Assisted Analog Predistortion Technique for Power ...

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88th ARFTG Microwave Measurement Conference (ARFTG) - Power Amplifiers and Systems Design for Wireless Application

作者： Gumber, Karan Jaraut, Praveen Rawat, Meenakshi Rawat, Karun Indian Inst Technol Dept Elect & Commun Engn Roorkee 247667 Uttar Pradesh India

ISBN: (纸本)9781509045143

This paper presents a digitally assisted analog-predistortion scheme for linearization of high power amplifier. Taking advantage of recent available digital signal processing solutions, the proposed method reduces hardware requirement of conventional analog predistorter by alleviating the need of Vector multiplier, hybrid 900 coupler and delay lines. Proposed method provides flexibility in terms of digitally compensation of delay, gain and phase control of signal. The proof-of-concept of method is presented for reducing odd-order intermodulation distortion (IMD). A better performance of 11-db reduction as compared to conventional analog predistorter in terms of 3rd IMD is achieved for two-tone test signal centered at frequency 2000 MHz and 2020 MHz.

关键词： Delay-lines field programmable gate array intermodulation distortion linearization power amplifiers rat race coupler

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High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two 24

High-Speed RTL Implementations and FPGA Benchmarking of Thre...

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24th IEEE International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Diehl, William Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9781509023561

Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs - the Xilinx Virtex-6 and Virtex-7. The authenticated ciphers chosen for this research are the CAESAR Round Two variants of SCREAM, POET, and Minalpher. To ensure standardization in evaluation, all three candidates are implemented with an identical version of a universal hardware API for authenticated ciphers. Results are compared against each other in terms of performance, area, and throughput-to-area (TP/A) ratio. SCREAM is found to have the highest TP/A ratio of these three ciphers.

关键词： Authentication cipher cryptography encryption field programmable gate array

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Bio inspired BFA optimization for Inductor less Voltage gain Converter

Bio inspired BFA optimization for Inductor less Voltage gain...

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International Conference on Energy Efficient Technologies for Sustainability (ICEETS)

作者： Sivakumar, A. Premalatha, L. VIT Univ Sch Elect Engn Madras 127 Tamil Nadu India

ISBN: (纸本)9781467399258

The proposed research work deals with the execution of BFOA control for switched capacitor converter (SCC) with closed loop performance analysis. The above-culled converter is incipiently developed novel DC to DC converter with voltage hoist technique. The dynamic behavioural characteristics of power electronic converters is exceedingly nonlinear due to the nature of switching operation and unstable nature of time and, hence BFOA predicated bio-inspired controller is introduced for the developed novel converter[Intelligent swarm optimization network was developed for the current research work]. The closed loop performance investigation of the above converter utilizing software simulation (MATLAB) and proto type implementation with FPGA was validated. For the conditions like supply perturbances and load transmutes the performance of the converter is found to be preponderant.

关键词： Switched Capacitor converter MATLAB Direct Current Bacterial foraging Algorithm field programmable gate array

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Fast Hardware Architectures for Supersingular Isogeny Diffie-Hellman Key Exchange on FPGA 17th

Fast Hardware Architectures for Supersingular Isogeny Diffie...

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17th International Conference on Cryptology in India (INDOCRYPT)

作者： Koziel, Brian Azarderakhsh, Reza Mozaffari-Kermani, Mehran Texas Instruments Inc Dallas TX 75243 USA I SENSE FAU CEECS Dept Boca Raton FL USA RIT EME Dept Rochester NY USA

ISBN: (纸本)9783319498904;9783319498898

In this paper, we present a constant-time hardware implementation that achieves new speed records for the supersingular isogeny Diffie-Hellman (SIDH), even when compared to highly optimized Haswell computer architectures. We employ inversion-free projective isogeny formulas presented by Costello et al. at CRYPTO 2016 on an FPGA. Modern FPGA's can take advantage of heavily parallelized arithmetic in F-p2 , which lies at the foundation of supersingular isogeny arithmetic. Further, by utilizing many arithmetic units, we parallelize isogeny evaluations to accelerate the computations of large-degree isogenies by approximately 57%. On a constant-time implementation of 124-bit quantum security SIDH on a Virtex-7, we generate ephemeral public keys in 10.6 and 11.6ms and generate the shared secret key in 9.5 and 10.8ms for Alice and Bob, respectively. This improves upon the previous best time in the literature for 768-bit implementations by a factor of 1.48. Our 83-bit quantum security implementation improves upon the only other implementation in the literature by a speedup of 1.74 featuring fewer resources and constant-time.

关键词： Post-quantum cryptography Elliptic curve cryptography Isogeny-based cryptography field programmable gate array

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