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检索条件"主题词=Field Programmable Gate array"

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An Efficient FPGA-Based Implementation of Predictive Current Control Algorithms for an Indirect Matrix Converter 8

An Efficient FPGA-Based Implementation of Predictive Current...

引用

8th IEEE International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia)

作者： Qi, Chen Tu, Pengfei Shi, Donghan Wang, Peng Zagrodnik, Michael A. Amit, Gupta Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore Rolls Royce Singapore Pte Ltd Singapore Singapore

ISBN: (纸本)9781509012107

To provide higher speed and more flexibility, this paper presents a new implementation method of predictive current control (PCC) algorithms for an indirect matrix converter (IMC) using a digital signal processor (DSP) and a field programmable gate array (FPGA). In this method, the SPARTAN-3E FPGA is used as a master controller to execute the PCC and commutation algorithms and the TMS320F28335 DSP is used as a slave controller to sample voltages and currents and then transmit all sampling results and synchronization signals to the FPGA. A programming structure consisting of a top module and several reusable sub-modules is designed in FPGA delivering reduced development time and better time/area efficiency. Experimental results from an IMC prototype confirmed the practical feasibility of proposed implementation method.

关键词： Digital signal processor field programmable gate array indirect matrix converter predictive current control

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SIMULATION OF BI-DIRECTIONAL DC-DC CONVERTER USING FPGA 7

SIMULATION OF BI-DIRECTIONAL DC-DC CONVERTER USING FPGA

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7th International Conference on Communication, Computing and Virtualization (ICCCV)

作者： Karthigeyan, P. Raja, M. Senthil Kumar, T. Siva Ganesh, S. R. Sivaa Lavanya, J. Indian Inst Technol Madras 600036 Tamil Nadu India VI Inst Technol Madras 603108 Tamil Nadu India KS Rangaswamy Coll Arts & Sci Madras 600119 Tamil Nadu India Sathyabama Univ Madras 600119 Tamil Nadu India

The basic idea of proposed system is to utilize the renewable resources by digital PWM control of Bi-directional DC - DC converter. Usually PWM pulse is being generated through a digital system such as microcontroller or Digital signal controller. In stand - alone application these controllers increases the cost but XILINX FPGA based PWM generation reduces the cost. XILINX FPGA is programmable device developed by XILINX which is being considered as an efficient device for rapid prototyping and also to perform concurrent operations. In this paper two PWM signals was generated to control the switch duty cycles in Bi-directional DC-DC Converter. In addition to that different modes of operation of the proposed circuit are verified by MATLAB / SIMULINK. (c) 2016 The Authors. Published by Elsevier B.V.

关键词： Bi-directional dc-dc converter pulse width modulation field programmable gate array XILINX duty cycle

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Stochastic Hardware Implementation of Liquid State Machines

Stochastic Hardware Implementation of Liquid State Machines

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International Joint Conference on Neural Networks (IJCNN)

作者： Alomar, Miquel L. Canals, Vincent Morro, Antoni Oliver, Antoni Rossello, Josep L. Univ Balear Isl Phys Dept Elect Engn Grp Palma de Mallorca Spain

ISBN: (纸本)9781509006199

The hardware implementation of neural network models allows to efficiently exploit their inherent parallelism. Here, we focus on the Liquid State Machine (LSM) methodology to build recurrent Spiking Neural Networks (SNN), particularly suited to process time-dependent signals. We propose a low cost hardware implementation of LSM networks based on the use of stochastic computing (SC) concepts. The functionality of the present approach is demonstrated for a time-series prediction task.

关键词： Spiking Neural Networks Recurrent Neural Networks Liquid State Machines Stochastic Computing field programmable gate array

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FPGA-Based Two-Processor CPU for PLC 9

FPGA-Based Two-Processor CPU for PLC

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International Conference on Signals and Electronic Systems (ICSES)

作者： Chmiel, Miroslaw Kloska, Wojciech Polok, Dariusz Mocha, Jan Silesian Tech Univ Inst Elect Gliwice Poland Inst Med Technol & Equipment 1TAM Zabrze Poland

ISBN: (纸本)9781509026678

The paper reveals a two-processor Central Processing Unit (CPU) designed for programmable Logic Controllers (PLC). The CPU is made up of a 1-bit (bit-type) processor and a 32-bit (word-type) processor. The both processors are operated totally independently from one another and information between them is exchanged via a exchange memory module. The 1-bit processor collaborates with edge detectors whilst the 32-bit processor is dedicated for implementation of timers and counters as well as enables execution of arithmetic operations on 32-bit integers and floating point variables. The both processors have been developed as specialized structures capable of executing control routines developed in the Instruction List (IL) programming language in line with requirements of the EN 61131-3 standard. The study presents a new approach to development of the exchange memory module and edge detectors as well as implementation of timers and counters. It is the approach that combines both software and hardware solutions, which makes them more efficient in terms of time performance as compared to already known solutions. Finally the CPU was designed with use of the hardware description language and then implemented in FPGA resources. This paper discloses results of the synthesis and execution times achieved for both individual instructions and benchmarks routines running on the newly designed CPU. The accomplished results make it possible to conclude that the CPU can be considered as an alternative solution to other units available from the market whilst the capability to execute algorithms developed in strict conformity to EN 61131-3 standard is its advantage.

关键词： Central Processing Unit programmable Logic Controller Programming Languages Instruction List programmable Logic field programmable gate array

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Implementation of a Novel Angular Hall Encoder for field Oriented Control of High Speed and Experimental Motors 17

Implementation of a Novel Angular Hall Encoder for Field Ori...

引用

17th International Conference on Mechatronics - Mechatronika (ME)

作者： Novak, Zdenek Novak, Martin Czech Tech Univ Dept Instrumentat & Control Engn Fac Mech Engn Tech 4 Prague 16607 Czech Republic

ISBN: (纸本)9788001058831

The aim of this paper is to investigate possibilities of an application of low-cost angular Hall encoder for an experimental high speed Permanent Magnet Synchronous Motor (PMSM). First, a brief overview of angular encoders is introduced. The possibilities of using standard types of sensors for PMSM are provided together with limits of their application. A recently introduced industrial angular Hall encoder iC-MH16, with a possibility of real time full resolution of 12-bits up to 200 000 rpm, is then presented. Its principle and a possible application range is described. This sensor is then applied to an industrial motor equipped with a regular position resolver. By reading the angular position from the output of both sensors, performance of Hall encoder is evaluated. After the evaluation, a new high speed experimental PMSM is designed with a possibility of using the introduced angular Hall encoder. This motor is then operated using field Oriented Control (FOC) fully implemented on the field programmable gate array (FPGA). The applied control algorithm is described as well, with a focus on timing requirements and optimization of FPGA resources.

关键词： angular Hall encoder field oriented control field programmable gate array permanent magnet motors

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An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA 29

An Improved Design of a Reversible Fault Tolerant LUT-Based ...

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29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID)

作者： Ul Haque, Mubin Sworna, Zarrin Tasnim Babu, Hafiz Md. Hasan Univ Dhaka Dept Comp Sci & Engn Dhaka 1000 Bangladesh

ISBN: (纸本)9781467387002

This paper presents the design of reversible fault tolerant architecture of logic elements of LUT ( look-up table) based field programmable gate array ( FPGA). The proposed logic elements are master slave Flip Flop, D-Latch and multiplexer. A new 4x4 and a new 6x6 fault tolerant reversible gates are proposed for designing efficient reversible fault tolerant D-latch, master slave Flip Flop and multiplexer, respectively. The design of the proposed logic elements achieve the improvement of 41.67% in terms of number of gates compared to the best known existing approach. Besides, the proposed logic elements outperform the best existing technology by 13.33% and 27.27% in terms of quantum cost and unit delay, respectively. Finally, the efficiency of the proposed elements are clarified by implementing an n-bit adder using the proposed Configurable Logic Block ( CLB) of FPGA with 60.9% power savings and 23.56% delay minimization.

关键词： Reversible logic Fault tolerant field programmable gate array Look-Up Table

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Implementation of Digital Lock-in Amplifier Based on System Generator

Implementation of Digital Lock-in Amplifier Based on System ...

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IEEE International Conference on Signal and Image Processing (ICSIP)

作者： Wang, Qingfeng Zheng, Hong Jiang, Meng Beijing Univ Aeronaut & Astronaut Sch Automat Sci & Elect Engn Beijing Peoples R China China Aerosp Sci & Technol Corp Res Acad 9 Res Inst 13 Beijing Peoples R China

ISBN: (纸本)9781509023776

Nowadays the weak signal detection technology is necessary in scientific research field, in which the phase-locked amplifying technology is widely used in the field of weak signal detection because it can meet the requirements of high speed and high accuracy. System Generator software is adopted as a tool since System Generator can make the design more conveniently and efficiently. The design of each module in orthogonal vector type digital phase-locked amplifier is introduced in this paper. The overall design was verified. The simulation results confirm that the design is feasible.

关键词： Weak signal Lock-in amplifier System Generator Orthogonal vector field programmable gate array

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Implementation of Crossbar switch for NOC on FPGA 3

Implementation of Crossbar switch for NOC on FPGA

引用

3rd International Conference on Computing for Sustainable Global Development (INDIACom)

作者： Virdi, Sukhbani Kaur Shekhar, Sushant Verma, Gaurav Maheshwari, Shikhar Srivastava, Oorja M. Jaypee Univ Dept Elect & Commun A-10Sect 62 Noida UP India Dept Elect & Commun Noida India

ISBN: (纸本)9789380544199

Now-a-days every electronics system, ranging from small mobile phone to satellite has SOC (System-on-chip). Over the years, SOC has undergone rapid evolution and are still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. In response to this crises, NOC (network-on-chip)is an upcoming archetype and is becoming a leading contender to replace conventional bus architectures. Many NOC topologies have been introduced in an attempt to tackle various chip architecture needs and routing technique. The mesh topology is well suited for incorporating regular size processing elements on single chip. It is also quite simpler to design and incorporate various routing protocols into it as opposed to others. Thus to validate the functioning of NOC on hardware, crossbar architecture has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA.

关键词： Network-on-chip System-on-chip VHDL field programmable gate array

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Software Defined Multi-Spectral Imaging for Arctic Sensor Networks 22

Software Defined Multi-Spectral Imaging for Arctic Sensor Ne...

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22nd SPIE Conference on Algorithms and Technologies for Multispectral, Hyperspectral, and Ultraspectral Imagery XXII

作者： Siewert, Sam Angoth, Vivek Krishnamurthy, Ramnarayan Mani, Karthikeyan Mock, Kenrick Singh, Surjith B. Srivistava, Saurav Wagner, Chris Claus, Ryan Vis, Matthew Demi Embry Riddle Aeronaut Univ Prescott 3700 Willow Creek Rd Prescott AZ 86301 USA Univ Colorado Campus Box 425 Boulder CO 80309 USA Arctic Domain Awareness Ctr 3211 Providence Dr Anchorage AK 99508 USA Univ Alaska Anchorage 3211 Providence Dr Anchorage AK 99508 USA

ISBN: (纸本)9781510600812

Availability of off-the-shelf infrared sensors combined with high definition visible cameras has made possible the construction of a Software Defined Multi-Spectral Imager (SDMSI) combining long-wave, near-infrared and visible imaging. The SDMSI requires a real-time embedded processor to fuse images and to create real-time depth maps for opportunistic uplink in sensor networks. Researchers at Embry Riddle Aeronautical University working with University of Alaska Anchorage at the Arctic Domain Awareness Center and the University of Colorado Boulder have built several versions of a low-cost drop-in-place SDMSI to test alternatives for power efficient image fusion. The SDMSI is intended for use in field applications including marine security, search and rescue operations and environmental surveys in the Arctic region. Based on Arctic marine sensor network mission goals, the team has designed the SDMSI to include features to rank images based on saliency and to provide on camera fusion and depth mapping. A major challenge has been the design of the camera computing system to operate within a 10 to 20 Watt power budget. This paper presents a power analysis of three options: 1) multi-core, 2) field programmable gate array with multi-core, and 3) graphics processing units with multi-core. For each test, power consumed for common fusion workloads has been measured at a range of frame rates and resolutions. Detailed analyses from our power efficiency comparison for workloads specific to stereo depth mapping and sensor fusion are summarized. Preliminary mission feasibility results from testing with off-the-shelf long-wave infrared and visible cameras in Alaska and Arizona are also summarized to demonstrate the value of the SDMSI for applications such as ice tracking, ocean color, soil moisture, animal and marine vessel detection and tracking. The goal is to select the most power efficient solution for the SDMSI for use on UAVs (Unoccupied Aerial Vehicles) and other drop-in-pl

关键词： software defined multi-spectral imager field programmable gate array general purpose graphics co-processor sensor fusion stereo vision long-wave infrared near-infrared Arctic saliency power efficient real-time

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Analysis of Radix-2 Decimation in Time Algorithm for FPGA Co-Processors 1

Analysis of Radix-2 Decimation in Time Algorithm for FPGA Co...

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International Conference on Computing, Electronic and Electrical Engineering (ICE Cube)

作者： Ibrahim, Muhammad Kamal, Mohsin Khan, Omar Ullah, Khalil Natl Univ Comp & Emerging Sci Dept Elect Engn Peshawar Pakistan Natl Univ Comp & Emerging Sci Dept Comp Sci Peshawar Pakistan

ISBN: (纸本)9781509012527

The Fast Fourier Transform (FFT) is a widely used algorithm for spectral analysis of signals and is widely used in applications of communications, biomedical signal processing, industrial process control, etc. Its wide usage and application has resulted in the implementation of a number of FFT algorithms for inputs of various sizes, dimensions, and platform types such as desktop computers, graphic cards, and special micro-processors. In this paper, a common but important FFT algorithm known as the radix-2 decimation in time (DIT) algorithm is implemented on a Spartan-6 FPGA kit using Xilinx ISE 14.2. The implementation is compared with various pre-installed IP-core modules of Xilinx for complex input of various sample sizes. The results show that our implementation of the radix-2 DIT algorithm for FPGA systems has not only a lower computation cost, less memory and resources utilization, but also provides better absolute error compared to the IP-core modules. A hardware synthesis is also provided.

关键词： Fast Fourier Transform field programmable gate array

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