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检索条件"主题词=Field Programmable Gate array"

共 1340 条记录，以下是741-750 订阅

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Gigabit Network Intrusion Detection System Using Extended Bloom Filter in Reconfigurable Hardware 2nd

Gigabit Network Intrusion Detection System Using Extended Bl...

引用

2nd International Conference on Computer and Communication Technologies

作者： Jose, Akshay Eldho Gireeshkumar, T. Amrita Vishwa Vidyapeetham TIFAC CORE Cyber Secur Coimbatore Tamil Nadu India

ISBN: (纸本)9788132225171;9788132225164

Network intrusion detection system collects information from network and identifies all the possible existing network security threats. Software based detection systems are common but are not good enough for the current network security requirements. Present day network intrusion detection needs wire-level data transfer to avoid the inefficiency in pattern matching process. Hardware based solutions like field programmable gate array which is known for its high processing capability can easily solve these issues. This paper implements a hardware based gigabit intrusion detection system using extended Bloom filter concepts. The paper presents a solution to reduce the high error rate of Bloom Filter by introducing a Reference Vector to the work and evaluates its performance. The reference vector verifies the Bloom filter output for any possible false positive results and reduces the error rate in the system.

关键词： Network intrusion detection field programmable gate array Extended bloom filter Reference vector

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The Modeling and Simulation for Current Regulation of PMSM Drive System using Verilog HDL and Variable Structure Control

The Modeling and Simulation for Current Regulation of PMSM D...

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International Automatic Control Conference (CACS)

作者： Lai, Chiu-Keng Tsai, Chia-Che Natl Chin Yi Univ Technol Dept Elect Engn Taichung Taiwan

ISBN: (纸本)9781509041091

In this study, we design the permanent magnet synchronous motor (PMSM) drive system using field programmable gate array (FPGA), and adopt variable structure control (VSC) to the current regulation. The system is first modeled with Matlab/Simulink, and the controllers in the system, including the speed PI control and current variable structure control, are hardware implemented by Verilog HDL code. Finally, the resulting hardware system is co-simulated with the software motor model to evaluate the accuracy and performance. The resulting Verilog HDL codes can be as an IP format to hardware realize the vector control for PMSM, and with the properties of robustness to the parameter variations and fast responses on the current loop control.

关键词： field programmable gate array Permanent Magnet Synchronous Motor Vector Control Variable Structure Control Verilog HDL

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GPlace: A Congestion-Aware Placement Tool for UltraScale FPGAs 35

GPlace: A Congestion-Aware Placement Tool for UltraScale FPG...

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35th IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

作者： Pattison, Ryan Abuowaimer, Ziad Areibi, Shawki Grewal, Gary Vannelli, Anthony Univ Guelph Sch Engn Guelph ON Canada Univ Guelph Sch Comp Sci Guelph ON Canada

ISBN: (纸本)9781450344661

Traditional FPGA flows that wait until the routing stage to tackle congestion are quickly becoming less effective. This is due to the increasing size and complexity of FPGA architectures and the designs targeted for them. In this paper, we present two new congestion-aware placement tools for Xilinx UltraScale architectures, called GPlace-pack and GPlace-flat, respectively. The former placer participated in the ISPD 2016 Routability-driven Placement Contest for FPGAs, and finished in third place overall. The latter placer was subseqently developed based on our experience in the contest with GPlace-pack. Results obtained indicate that GPlace-flat is on average 5.3x faster than GPlace-pack. The post routing results show that GPlace-flat is able to obtain a further 22.5% improvement in wirelength and a 40.0% improvement in runtime compared to GPlace-pack.

关键词： Placement field programmable gate array Congestion Routing-aware Heterogeneous UltraScale Architecture

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FPGA-Based System Level Design of Control Systems: A Case Study of Three-Axis Positioning Controller Implementation

FPGA-Based System Level Design of Control Systems: A Case St...

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International Conference on New Trends in Signal Processing (NTSP)

作者： Stankovic, Momir Manojlovic, Stojadin Simic, Slobodan Mitrovic, Srdjan Naumovic, Milica Univ Def Mil Acad Belgrade Serbia Univ Nis Fac Elect Engn Nish Serbia

ISBN: (纸本)9788080405298

In this paper field programmable gate array (FPGA) system level based methodology for control system design is proposed and described in details on the case study of three-axis positioning controller implementation. System level design tool, such as Xilinx System Generator (XSG), provides Simulink based FPGA design and automatic converting of XSG model into efficient Very high speed integrated circuit Hardware Description Language (VHDL) code, increasing productivity by reducing the design time. The optimal design, in terms of FPGA recourse occupancy, is provided using restructuring data flow graph (DFG) of control algorithm and specifying the optimal fixed-point format. The proposed approach is validated through real experiments on three-axis didactic radar platform.

关键词： field programmable gate array Xilinx System Generator optimized design position control

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Investigations of Power and EM Attacks on AES Implemented in FPGA 5th

Investigations of Power and EM Attacks on AES Implemented in...

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5th International Conference on Soft Computing for Problem Solving (SocProS)

作者： Singh, Arvind Kumar Mishra, S. P. Suri, B. M. Khosla, Anu Minist Def DRDO SAG Metcalfe House Delhi 110054 India

ISBN: (纸本)9789811004513;9789811004506

Side-channel attack is a new area of research which exploits the leakages such as power consumption, execution time, EM radiation, etc., of crypto algorithms running on electronic circuitry to extract the secret key. This paper describes the VHDL implementations of Advanced Encryption Standard (AES) algorithm on field programmable gate array board (Spartan 3E) employing Xilinx tool and discusses briefly about Correlation Power/EM Analysis attacks. These attacks have been mounted on part of power and EM traces corresponding to tenth round of AES algorithm. Power and EM traces are being acquired using current probe and EM probe station respectively with the help of oscilloscope and PC. Effects of different ways of implementations on these attacks have been explored. Studies have been carried out to find the effect of operating frequencies and number of samples per clock on the computational complexities in terms of number of traces required to extract the key.

关键词： Side Channel Attack Advanced Encryption Standard Correlation Power Attack Correlation EM Attack field programmable gate array

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Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-based Systems 30

Resource-Efficient Scheduling for Partially-Reconfigurable F...

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30th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Purgato, Andrea Tantillo, Davide Rabozzi, Marco Sciuto, Donatella Santambrogio, Marco D. Politecn Milan Milan Italy

ISBN: (纸本)9781509036820

In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based systems that allows to achieve high quality results in terms of overall application execution time. The proposed algorithm exploits the notion of resource efficient task implementations in order to reduce the overhead incurred by partial dynamic reconfiguration and increase the number of concurrent tasks that can be hosted on the reconfigurable logic as hardware accelerators. We evaluate a fast deterministic version of the scheduler that is able to find good quality solutions in a small amount of time and a randomized version of the approach that can be executed multiple times to improve the final result.

关键词： field programmable gate array Partial Dynamic Reconfiguration Reconfigurable Architectures Scheduling System on Chip

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RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two 19

RTL Implementations and FPGA Benchmarking of Three Authentic...

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19th Euromicro Conference on Digital System Design (DSD)

作者： Diehl, William Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9781509028160

Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs. The authenticated ciphers chosen for this research are the CAESAR Round Two variants of SCREAM, POET, and Minalpher. Ciphers are discussed from an engineering standpoint, and are compared and contrasted in terms of design features. To ensure conformity and standardization in evaluation, all three candidates are implemented with an identical version of the CAESAR Hardware API for authenticated ciphers. Functionally correct implementations of all three ciphers are realized, and results are compared against each other and previous results in terms of throughput, area, and throughput-to-area (T/A) ratio. SCREAM is found to have the highest T/A ratio of these three ciphers in the Virtex-6 FPGA, while Minalpher has the highest T/A ratio in the Virtex-7 FPGA.

关键词： Authentication cipher cryptography encryption field programmable gate array

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An Analytical Approach for Estimation of Single Event Transients

An Analytical Approach for Estimation of Single Event Transi...

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IEEE International Conference on Emerging Technological Trends in Computing, Communications and Electrical Engineering (ICETT)

作者： Suseelan, Surya Mohan, Pooja S. Sree Buddha Coll Engn Elect & Commun Dept Pattoor Alappuzha India

ISBN: (纸本)9781509037513

Transient faults are a matter of increasing concern as advanced technologies scales to smaller and smaller feature technologies. Transient errors are random faults of the hardware, which also called as soft errors. Single Event Transients (SETs) are major part of the error events which will continue to grow in the next technology nodes and affect the system functionality. Varieties of electronic products are coming into market and most of them are incorporated with large memory components, which will lead to an increase in error rates. This paper presents a very fast and accurate technique to estimate the soft error rate of digital circuits in the occurrence of Single Event Transients (SETs). Analytical approach is implemented in the proposed method to estimate the total failure rate probability along different paths in a design which includes node error rate and error propagation error rate. Paper computed the probability that a hit at any gate has an impact in the desired function of the model and is implemented using path construction, topological sorting and propagation rules. Experiment on a circuit and comparison of the results with cube based error propagation probability(EPP) analysis showed that the proposed method shows more accurate evaluation in error rate estimation of a designed model. Implementation of the proposed system helps the designers to examine the gate-level designs and also provide detailed individual contribution of each gate that are vulnerable to soft errors.

关键词： Cube based EPP analysis field programmable gate array multiple event transients ordering path construction propagation rules

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A System-Level Design for Foreground and Background Identification in 3D Scenes

A System-Level Design for Foreground and Background Identifi...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Safaei, Amin Wu, Q. M. Jonathan Univ Windsor Dept Elect & Comp Engn Windsor ON Canada

ISBN: (纸本)9781479953417

This paper proposes a system-on-chip (SoC) FPGA - based real-time video processing platform for background and foreground identification. Background and foreground identification is a common feature in many tasks in video content analytics (VCA), including object detection, tracking, segmentation and recognition. VCA is a relatively new field in video processing;it has generally been implemented using two chips, with the image signal processing (ISP) part in a DSP or an FPGA and the VCA part executed by a processor. However, a new generation of SoC FPGAs that incorporates a processor and an FPGA into a single chip makes it possible for a single chip to perform both ISP and VCA. This study details the hardware implementation of a real-time background and foreground identification algorithm in an SoC, including the capture, processing and display stages. The proposed platform uses photometric invariant color, depth data and local binary patterns (LBPs) to distinguish backgrounds from foregrounds. The system uses minimal cell resources and tries to implement modules using a pipeline technique.

关键词： Real time video processing field programmable gate array embedded vision subtraction techniques

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Structural Modification based Netlist Obfuscation Technique for PLDs

Structural Modification based Netlist Obfuscation Technique ...

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IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)

作者： Sumathi, G. Srivani, L. Murthy, D. Thirugnana Kumar, Anish Madhusoodanan, K. Murty, S. A. V. Satya Homi Bhabha Natl Inst Kalpakkam 603102 Tamil Nadu India Indira Gandhi Ctr Atom Res Kalpakkam 603102 Tamil Nadu India

ISBN: (纸本)9781467393379

Logic obfuscation is widely followed in intellectual property cores and chip designs as hardware protection mechanism against design security threats such as reverse engineering (RE), piracy, cloning, overbuilding, etc. In general, sequential obfuscation has two modes of operation such as obfuscated and functional modes. Finite state machines (FSM) are being used to implement the mode control. When a specific sequence of input vectors is applied during power up for user authentication, the circuit will enter into functional mode. Otherwise, FSM remains in obfuscated mode and do not perform the intended functionality. In general, hardware obfuscation technique is applicable to all programmable logic devices. However, we applied the structural modification based netlist obfuscation methodology to field programmable gate array devices. The software implementation of sequential obfuscation is performed for a set of ISCAS'89 benchmark circuits using Libero IDE v9.1 on Actel device. As simulation/structural analysis are the conventional methods to perform RE, we aimed to achieve a high percentage of simulation / structural mismatch during RE. We presented two scenarios of obfuscation: 1) For better structural mismatch during RE, insertion of obfuscation cells at different numbers of high fanout (HF) nets with minimum initialization sequence length (L). As per the designer's area constraint, the total number of nets to be obfuscated is chosen. 2) For better functional simulation mismatch during RE, FSM with different L values is included in the design with a minimum number of obfuscation cells. The initialization sequence length is decided concerning the system clock cycle (i.e. delay constraint). Based on the control signals derived from FSM, the values at HF obfuscated nets are decided. That is, the circuit executes the required functionality only in the functional mode. Hence, the simulation/structural RE complexity of PLDs is improved. This paper discusses the simulati

关键词： field programmable gate array Obfuscation Reverse engineering

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