Logic obfuscation is widely followed in intellectual property cores and chip designs as hardware protection mechanism against design security threats such as reverse engineering (RE), piracy, cloning, overbuilding, et...
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ISBN:
(纸本)9781467393379
Logic obfuscation is widely followed in intellectual property cores and chip designs as hardware protection mechanism against design security threats such as reverse engineering (RE), piracy, cloning, overbuilding, etc. In general, sequential obfuscation has two modes of operation such as obfuscated and functional modes. Finite state machines (FSM) are being used to implement the mode control. When a specific sequence of input vectors is applied during power up for user authentication, the circuit will enter into functional mode. Otherwise, FSM remains in obfuscated mode and do not perform the intended functionality. In general, hardware obfuscation technique is applicable to all programmable logic devices. However, we applied the structural modification based netlist obfuscation methodology to field programmable gate array devices. The software implementation of sequential obfuscation is performed for a set of ISCAS'89 benchmark circuits using Libero IDE v9.1 on Actel device. As simulation/structural analysis are the conventional methods to perform RE, we aimed to achieve a high percentage of simulation / structural mismatch during RE. We presented two scenarios of obfuscation: 1) For better structural mismatch during RE, insertion of obfuscation cells at different numbers of high fanout (HF) nets with minimum initialization sequence length (L). As per the designer's area constraint, the total number of nets to be obfuscated is chosen. 2) For better functional simulation mismatch during RE, FSM with different L values is included in the design with a minimum number of obfuscation cells. The initialization sequence length is decided concerning the system clock cycle (i.e. delay constraint). Based on the control signals derived from FSM, the values at HF obfuscated nets are decided. That is, the circuit executes the required functionality only in the functional mode. Hence, the simulation/structural RE complexity of PLDs is improved. This paper discusses the simulati
A synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. The method can be easily included in designi...
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ISBN:
(纸本)9783319453774;9783319453781
A synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. The method can be easily included in designing the flow of digital systems in FPGA. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The experimental results showed a high efficiency of the offered method. FSM performance increases by 1.52 times on occasion. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.
Masking is a proven countermeasure to protect physical cryptographic implementations against power analysis side-channel attacks, such as differential power analysis (DPA). Boolean masking is one of several types of m...
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ISBN:
(纸本)9781509028160
Masking is a proven countermeasure to protect physical cryptographic implementations against power analysis side-channel attacks, such as differential power analysis (DPA). Boolean masking is one of several types of masking schemes that can be added to a cipher to increase its security. However, implementing a secure and efficient Boolean masking scheme across all components of a cipher, including non-linear transformations, can be challenging. In this research, a 1st order Boolean masking scheme is applied to the SCREAM authenticated cipher, a CAESAR Round Two candidate. The non-masked and masked versions of the full authenticated cipher are implemented in the Virtex-6 FPGA and compared in terms of throughput, area, and throughput-to-area (T/A) ratio. The SCREAM block cipher is then compared to a masked version of AES to determine the relative costs of masking among the two ciphers. The results show that the T/A ratio of the masked SCREAM full authenticated cipher is only 50% of the T/A ratio of the non-masked version, and that the masking cost of the SCREAM block cipher is roughly equal to that of an equivalently-masked version of the AES block cipher.
The Total Ionizing Dose (TID) tolerance of some FPGAs and memory devices has been evaluated. Two FPGAs and five memories of various types and technologies have been irradiated. Results show that the total dose toleran...
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ISBN:
(纸本)9781509002320
The Total Ionizing Dose (TID) tolerance of some FPGAs and memory devices has been evaluated. Two FPGAs and five memories of various types and technologies have been irradiated. Results show that the total dose tolerance of the tested FPGAs is around 200 Gy. The SRAM is the most tolerant device with a failure dose level over 2.4 kGy. Two Flash memories were still well-functioning after 1 kGy.
Model checking is a widely used technique to prove properties such as liveness, deadlock or safety for a given model. Here we introduce model checking of reconfigurable Petri nets. These are Petri nets with a set of r...
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ISBN:
(纸本)9783319405308;9783319405292
Model checking is a widely used technique to prove properties such as liveness, deadlock or safety for a given model. Here we introduce model checking of reconfigurable Petri nets. These are Petri nets with a set of rules for changing the net dynamically. We obtain model checking by converting reconfigurable Petri nets to specific Maude modules and using then the LTLR model checker of Maude. The main result of this paper is the correctness of this conversion. We show that the corresponding labelled transitions systems are bisimular. In an ongoing example reconfigurable Petri nets are used to model and to verify partial dynamic reconfiguration of field programmable gate arrays.
The Solar Probe Plus mission, under NASA's Living With a Star Program, will fly a spacecraft (S/C) through the sun's outer corona with orbit perihelia that gradually approach as close as 9.86 solar radii from ...
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ISBN:
(数字)9781624104077
ISBN:
(纸本)9781624104077
The Solar Probe Plus mission, under NASA's Living With a Star Program, will fly a spacecraft (S/C) through the sun's outer corona with orbit perihelia that gradually approach as close as 9.86 solar radii from the center of the sun. The mission will gather data on the processes of coronal heating, solar wind acceleration and production, and evolution and transport of solar energetic particles. The S/C is powered by two actively cooled photovoltaic solar array (S/A) wings. A novel power system electronics (PSE) box facilitates power delivery to the S/C in a tightly packaged, single-fault-tolerant system. The PSE contains a central digital controller to maximize power throughput from the S/A while protecting the battery, S/A, and downstream loads. The PSE is configurable and scalable up to 900-W output power. A novel grounding and isolation scheme is presented with the detailed architecture and digital control implementation.
The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. Th...
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The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA-ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA-ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and doing successive hypothesis tests. The proposed detector does not require any prior information about the background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. Recent advances in FPGA technology and availability of sophisticated design tools have made it possible to realise the computation intensive ACCA-ODV detector in hardware, in a cost-effective way. The architecture is modular and has been implemented and tested on an Altera Stratix II FPGA using Quartus II software. The post place and route result show that the proposed design can operate at 100 MHz, the maximum clock frequency of the prototyping board and for this frequency the total processing time required to perform a single run is 0.21 mu s. This amounts to a speedup for the FPGA-based hardware implementation by a factor of similar to 110 as compared to software-based implementation, which takes 23 mu s to perform the same operation.
A system for determining vehicle attitude using a field programmable gate array and low-cost gyroscopes is presented. The method is intended to support the stabilization of a short duration, unmanned aerial vehicle. U...
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A system for determining vehicle attitude using a field programmable gate array and low-cost gyroscopes is presented. The method is intended to support the stabilization of a short duration, unmanned aerial vehicle. Using a microelectromechanical system inertial sensor for the calibration and serial interface, the algorithm sidesteps concerns related to electromagnetic interference and the impact of embedded, proprietary filters. An Allan variance analysis is used to characterize the sensor errors and predict system performance. A floating point representation using a direction cosine matrix is hosted on the field programmable gate array alongside the platform stabilization feedback loops. Although prone to drifting without additional aiding, the derived attitude has been demonstrated to be effective in stabilizing a remotely piloted quadrotor.
As safety and reliability critical components, lithium-ion batteries always require real-time diagnosis and prognosis. This often involves a large amount of computation, which makes diagnosis and prognosis difficult t...
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As safety and reliability critical components, lithium-ion batteries always require real-time diagnosis and prognosis. This often involves a large amount of computation, which makes diagnosis and prognosis difficult to implement, especially in embedded or mobile applications. To address this issue, this paper proposes a run-time Reconfigurable Computing (RC) system on field programmable gate array (FPGA) for Relevance Vector Machine (RVM) to realize real-time Remaining Useful Life (RUL) estimation. The system leverages state-of-the-art run-time dynamic partial reconfiguration technology and customized computing circuits to balance the hardware occupation and computing efficiency. Optimal hardware resource consumption is achieved by partitioning the RVM algorithm according to a multi-objective optimization. Moreover, pipelined and parallel computation circuits for kernel function and matrix inverse are proposed on FPGA to further accelerate the computation. Experimental results with two different battery data sets show that, without sacrificing the RUL prediction performance, the embedded RC platform significantly reduces the computation time and the requirement of hardware resources. This demonstrates that complex prognostic tasks can be implemented and deployed on the proposed system, and it can be extended to the embedded computation of other machine learning algorithms.
This paper describes the design and field programmable gate array (FPGA) based 4 × 4 breadth heuristic Multiple-Input—Multiple-Output (MIMO) decoder using 16 and 64 Quadrature Amplitude Modulation (QAM) schemes....
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This paper describes the design and field programmable gate array (FPGA) based 4 × 4 breadth heuristic Multiple-Input—Multiple-Output (MIMO) decoder using 16 and 64 Quadrature Amplitude Modulation (QAM) schemes. The intention of this work is to observe the performance of Candidate Execution with Low Latency Approach for soft MIMO detector in FPGA (CELLA). The Smart Ordering and Candidate Adding (SOCA), Parallel Candidate Adding (PCA) and Backward Candidate Adding (BCA) give better performance in terms of Bit Error Rate (BER) or chip level service. In order to attain both BER and FPGA level performance in a single system, CELLA is developed in this work. Simulation and experimental results demonstrate the effectiveness of the proposed work under the system 4 × 4 MIMO-OFDM employing 16 QAM and 64 QAM. The proposed experiment is implemented in Xilinx Virtex 5 C5VSX240T. The performance results, in terms of FPGA level 76% slice reduction, 58.76% throughput improvement, 75% power reduction and 87% latency reduction, are achieved. The BER performance is observed and compared with the conventional algorithms. Thus, the proposed work achieves better outcome than the conventional work.
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