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International Conference on Intelligent Sustainable Systems

作者： Sudhakar Ajmera Mahendra Vucha Aruna Kokkula Department of Electronics and Communication Engineering MLR Institute of Technology Hyderabad India Dept. of ECE Matrusri Engineering College Hyderabad India

ISBN: (纸本)9781538619605

The orthogonal code is one of the error correction and detection codes and it can detect errors and correct corrupted data. An n-bit orthogonal code would haven/2 1's and n/2 0's and these properties can effectively participate in detecting and correcting the errors. Thus this article presents a new methodology to enable error detection capabilities using the orthogonal code. The orthogonal codes has been verified experimentally and proved their physical reliability by implementing on field programmable gate arrays (FPGA). The experimental results shows that the proposed orthogonal code can improve the detection capabilities of the transmitted informationup to 99.9% and also it corrects errors up to (n/2 - 1) bits in the received information with bandwidth efficiency.

关键词： Orthogonal Code Cyclic Redundancy Check field programmable gate array

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Soft Core Processor Generated Based on the Machine Code of the Application

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2016年第4期25卷 1650029-1650029页

作者： Ziebinski, Adam Swierc, Stanwlaw Silesian Tech Univ Inst Informat Fac Automat Control Elect & Comp Sci Akademicka 16 PL-44100 Gliwice Poland

Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4).

关键词： Application-specific instruction processor field programmable gate array hardware description language soft core processor generator

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Optical methods of the delay cells characteristics measurements and their applications

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OPTICAL AND QUANTUM ELECTRONICS 2016年第3期48卷 188-188页

作者： Frankowski, Robert Gurski, Maciej Plociennik, Przemyslaw Nicholas Copernicus Univ Inst Phys Fac Phys Astron & Informat Grudziadzka 5 PL-87100 Torun Poland

The only efficient optical spectrum measurement in infra-red range for low light regime is based on time multiplexing. Typically low timing jitter of the single photon detector combined with fast and high precision electronics is used for photon arrival time measurement. The timing histogram can be used to determine the spectrum of the photons. The better time detection accuracy allows to obtain the more precise spectrum information. This paper proposed an optical method for the sub-picosecond time-to-digital converters characterization prefer to optimize the multi-tapped delay lines implementation process, thus yielding the converters with much improved parameters.

关键词： Optical delay line field programmable gate array Time-interval measurement Delay cells Optical and quantum measurements

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Design and FPGA-Implementation of Minimum PED Based K-Best Algorithm in MIMO Detector

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Circuits and Systems 2016年第6期7卷 612-621页

作者： Poornima Ramasamy Mahabub Basha Ahmedkhan Mounika Rangasamy Department of ECE K.S.R. College of Engineering Tiruchengode India

Minimum Partial Euclidean Distance (MPED) based K-best algorithm is proposed to detect the best signal for MIMO (Multiple Input Multiple Output) detector. It is based on Breadth-first search method. The proposed algorithm is independent of the number of transmitting/receiving antennas and constellation size. It provides a high throughput and reduced Bit Error Rate (BER) with the performance close to Maximum Likelihood Detection (MLD) method. The main innovations are the nodes that are expanded and visited based on MPED algorithm and it keeps track of finally selecting the best candidates at each cycle. It allows its complexity to scale linearly with the modulation order. Using Quadrature Amplitude Modulation (QAM) the complex domain input signals are modulated and are converted into wavelet packets and these packets are transmitted using Additive White Gaussian Noise (AWGN) channel. Then from the number of received signals the best signal is detected using MPED based K-best algorithm. It provides the exact best node solution with reduced complexity. The pipelined VLSI architecture is the best suited for implementation because the expansion and sorting cores are data driven. The proposed method is implemented targeting Xilinx Virtex 5 device for a 4 × 4, 64-QAM system and it achieves throughput of 1.1 Gbps. The results of resource utilization are tabulated and compared with the existing algorithms.

关键词： Multiple Input Multiple Output Detector K-Best Algorithm Partial Euclidean Distance Quadrature Amplitude Modulation field programmable gate array

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FPGA Implementation of Approximate 2D Discrete Cosine Transforms

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Circuits and Systems 2016年第4期7卷 434-445页

作者： M. Thiruveni Raguraman D. Shanthi Saravanan Department of ECE Department of CSE PSNA College of Engineering and Technology Dindigul India

Discrete cosine transform (DCT) is frequently used in image and video signal processing due to its high energy compaction property. Humans are able to perceive and identify the information from slightly erroneous images. It is enough to produce approximate outputs rather than absolute outputs which in turn reduce the circuit complexity. Numbers of applications like image and video processing need higher dimensional DCT algorithms. So the existing architectures of one dimensional (1D) approximate DCTs are reviewed and extended to two dimensional (2D) approximate DCTs. Approximate 2D multiplier-free DCT architectures are coded in Verilog, simulated in Modelsim to evaluate the correctness, synthesized to evaluate the performance and implemented in virtexE field programmable gate array (FPGA) kit. A comparative analysis of approximate 2D DCT architectures is carried out in terms of speed and area.

关键词： Discrete Cosine Transform Energy Compaction field programmable gate array Dimension

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Selection of an Optimum Entropy Source Design for a True Random Number Generator

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Procedia Technology 2016年 25卷 598-605页

作者： Lakshmi Sreekumar P. Ramesh P G Scholar College of Engineering Munnar Idukki Pin 685612 India Associate professor College of Engineering Munnar Idukki Pin 685612 India

Random number generators are a vital component in many cryptographic algorithms and systems, such as generation of keys in secret key cryptography and public key cryptography. For cryptographic applications, True Random Number Generator utilizes unpredictability as the key component. Insufficient entropy produces predictable keys, so the major concern is to have a better entropy source. Entropy source which is based on a delay chain structure is presented in this paper. Here the randomness is generated by the timing differential existing between the clock and the data signal. In this design the delays are adjusted so that the data can be sampled at the limit of switching point The proposed design is very simple as it is based on a loop structure which does not contain any complex structures like Delay Locked Loop (DLL).

关键词： Entropy Metastability field programmable gate array

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Simulation of Bi-directional DC-DC Converter Using FPGA

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Procedia Computer Science 2016年 79卷 708-714页

作者： P. Karthigeyan M Senthil Raja T Siva Kumar S.R Sivaa Ganesh J. Lavanya Research Scientist I.I.T Madraschennai-600036 India Assistant Professor VI Institute of technology chennai-603108 India UG scholar KS Rangaswamy college of arts and sciencechennai-600119 UG scholar Sathyabama Universitychennai-600119

The basic idea of proposed system is to utilize the renewable resources by digital PWM control of Bi-directional DC – DC converter. Usually PWM pulse is being generated through a digital system such as microcontroller or Digital signal controller. In stand – alone application these controllers increases the cost but XILINX FPGA based PWM generation reduces the cost. XILINX FPGA is programmable device developed by XILINX which is being considered as an efficient device for rapid prototyping and also to perform concurrent operations. In this paper two PWM signals was generated to control the switch duty cycles in Bi-directional DC-DC Converter. In addition to that different modes of operation of the proposed circuit are verified by MATLAB / SIMULINK.

关键词： Bi-directional dc-dc converter pulse width modulation field programmable gate array XILINX duty cycle.

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FPGA based digital phase-coding quantum key distribution system

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Science China(Physics,Mechanics & Astronomy) 2015年第12期58卷 153-159页

作者： LU XiaoMing Zhang LiJun WANG YongGang CHEN Wei HUANG DaJun LI Deng WANG Shuang HE DeYong YIN ZhenQiang ZHOU Yu HUI Cong HAN ZhengFu Department of Modern Physics University of Science and Technology of China Key Laboratory of Quantum Information University of Science and Technology of China Synergetic Innovation Center of Quantum Information & Quantum Physics University of Science and Technology of China Chinese Academy of Sciences

Quantum key distribution （QKD） is a technology with the potential capability to achieve information-theoretic security. Phase- coding is an important approach to develop practical QKD systems in fiber channel. In order to improve the phase-coding modulation rate, we proposed a new digital-modulation method in this paper and constructed a compact and robust prototype of QKD system using currently available components in our lab to demonstrate the effectiveness of the method. The system was deployed in laboratory environment over a 50 km fiber and continuously operated during 87 h without manual interaction. The quantum bit error rate （QBER） of the system was stable with an average value of 3.22% and the secure key generation rate is 8.91 kbps. Although the modulation rate of the photon in the derno system was only 200 MHz, which was limited by the Faraday- Michelson interferometer （FMI） structure, the proposed method and the field programmable gate array （FPGA） based electronics scheme have a great potential for high speed QKD systems with Giga-bits/second modulation rate.

关键词： quantum key distribution phase-coding digital phase modulation field programmable gate array Faraday-Michelsoninterferometer

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Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

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IET COMPUTERS AND DIGITAL TECHNIQUES 2015年第4期9卷 190-196页

作者： Trefzer, Martin A. Walker, James A. Bale, Simon J. Tyrrell, Andy M. Univ York Dept Elect York YO10 5DD N Yorkshire England

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs.

关键词： flip-flops MOSFET field programmable gate arrays D-type flip-flop timing characteristics intrinsic stochastic variability design optimisation case study technology process multireconfigurable architecture field programmable gate array next-generation FPGA architecture gate level transistor level configuration options hardware VLSI prototype virtual prototype simulation program integrated circuit emphasis statistically enhanced high performance metal gate MOSFET compact models gold standard simulations prefabrication verification programmable analogue architecture digital array architecture post-fabrication transistor-level optimisation operating point size 25 nm

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An Efficient FPGA based Real-Time Implementation Shunt Active Power Filter for Current Harmonic Elimination and Reactive Power Compensation

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JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY 2015年第4期10卷 1655-1666页

作者： Charles, S. Vivekanandan, C. Sri Shakthi Inst Engn & Technol Dept Elect & Elect Engn Coimbatore Tamil Nadu India SNS Coll Engn Dept Elect & Elect Engn Coimbatore Tamil Nadu India

This paper proposes a new approach of field programmable gate array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

关键词： Digital control Shunt active power filter field programmable gate array Harmonic elimination Reactive power compensation Synchronous reference frame transformation

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