Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is...
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Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 mu m crystalline oxide semiconductor FET on a 0.5 mu m CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.
Grid connected power converters are widely used to interface between grid - on one side- and loads or renewable energy sources - on the other side. This work presents an indirect sliding mode power control (ISMPC) for...
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Grid connected power converters are widely used to interface between grid - on one side- and loads or renewable energy sources - on the other side. This work presents an indirect sliding mode power control (ISMPC) for three phase grid connected power converter. This control is characterised by improved robustness with regard to external disturbances and parameters changes, while insuring at the same time low current total harmonic distortion factor. The development and implementation of the ISMPC algorithm on low cost Microsemi SmartFusion digital solution is also described. This digital solution includes in the same chip a field programmable gate array (FPGA) fabric and a Cortex-M3 processor associated to large number of peripheral cores. The developed ISMPC is compared with standard and commonly used controls for grid connected converters to show its interest and advantages. Moreover, an overview of the experimental set-up, the description of the algorithm modular partitioning between FPGA and processor, the resources optimisation as well as the execution time reduction are presented. Selected experimental results corresponding to different operation steps are presented to illustrate performances and effectiveness of the proposed ISMPC algorithm.
The proposed research work deals with the execution of BFOA control for switched capacitor converter (SCC) with closed loop performance analysis. The above-culled converter is incipiently developed novel DC to DC conv...
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ISBN:
(纸本)9781467399265
The proposed research work deals with the execution of BFOA control for switched capacitor converter (SCC) with closed loop performance analysis. The above-culled converter is incipiently developed novel DC to DC converter with voltage hoist technique. The dynamic behavioural characteristics of power electronic converters is exceedingly nonlinear due to the nature of switching operation and unstable nature of time and, hence BFOA predicated bio-inspired controller is introduced for the developed novel converter [Intelligent swarm optimization network was developed for the current research work]. The closed loop performance investigation of the above converter utilizing software simulation (MATLAB) and proto type implementation with FPGA was validated. For the conditions like supply perturbances and load transmutes the performance of the converter is found to be preponderant.
The execution speed of a programmable logic controller (PLC) depends upon the number of analog and digital input it scans, complication in ladder diagram and the time to store the ladder diagram outputs in memory. Nex...
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The execution speed of a programmable logic controller (PLC) depends upon the number of analog and digital input it scans, complication in ladder diagram and the time to store the ladder diagram outputs in memory. Next to the ladder diagram, scanning of analog signals consume enough time as they have to be converted into digital. The two facts that limit the conversion speed is that the processor used for analog signal scanning can process only one channel at a time and the multichannel analog to digital converter (ADC) has digital output for only one channel. The hardware nature of field programmable gate array (FPGA) allows simultaneous conversion of all the analog signals into digital and storage of digital data in block RAM. The proposed design discusses the design of multichannel ADC using FPGA. The simulation result shows that the conversion time of 'n' channel ADC is 13.17 mu s. This increases the PLC execution speed. (C) 2014 Elsevier B.V. All rights reserved.
FPGA-based genetic algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design...
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FPGA-based genetic algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design experience, this study proposes a general-purpose automated framework for creating and executing a GA system on FPGAs. This framework contains scalable and customisable hardware architectures while providing a unified platform for different chromosomes. At compile-time, only a high-level input of the target application needs to be provided, without any hardware-specific code being necessary. At run-time, application inputs and GA parameters can be tuned, without time-consuming recompilation, for finding further good configurations of GA execution. The framework was tested on a high performance FPGA platform using nine problems and benchmarks, including the travelling salesman problem, a locating problem and the NP-hard set covering problem. Experiments show the system's flexibility and an average speedup of 29 times over a multi-core CPU.
This paper proposes a system-on-chip (SoC) FPGA - based real-time video processing platform for background and foreground identification. Background and foreground identification is a co mmon feature in many tasks in ...
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ISBN:
(纸本)9781479953424
This paper proposes a system-on-chip (SoC) FPGA - based real-time video processing platform for background and foreground identification. Background and foreground identification is a co mmon feature in many tasks in video content analytics (VCA), including object detection, tracking, segmentation and recognition. VCA is a relatively new field in video processing;it has generally been implemented using two chips, with the image signal processing (ISP) part in a DSP or an FPGA and the VCA part executed by a processor. However, a new generation of SoC FPGAs that incorporates a processor and an FPGA into a single chip makes it possible for a single chip to perform both ISP and VCA. This study details the hardware implementation of a real-time background and foreground identification algorithm in an SoC, including the capture, processing and display stages. The proposed platform uses photometric invariant color, depth data and local binary patterns (LBPs) to distinguish backgrounds from foregrounds. The system uses minimal cell resources and tries to implement modules using a pipeline technique.
Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors int...
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Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partially-parallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix. The proposed architecture is resource efficient, provides scalable throughput and requires substantially less power compared to other decoders reported to date. The proposed decoder has been implemented on a Xilinx FPGA suitable for WiMAX application and achieves a throughput of 548 Mbps. Performance evaluation of the decoder has been carried out by transmitting JPEG images over a wireless noisy channel and comparing the quality of the reconstructed images with those from other similar decoders. (C) 2014 Elsevier B.V. All rights reserved.
A small-scale electric model vehicle is built with four in-wheel motors. A field programmable gate array is chosen as the control kernel for this electric vehicle system. Since this electric model vehicle has four in-...
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A small-scale electric model vehicle is built with four in-wheel motors. A field programmable gate array is chosen as the control kernel for this electric vehicle system. Since this electric model vehicle has four in-wheel driving motors without differential mechanism, it needs an electronic differential and well-designed control algorithm to manipulate the vehicle driving speed and orientation. Accurate mathematical model of this multi-input and multi-output electric vehicle system is difficult to establish for a model-based controller design. Here, the adaptive functional approximation control scheme is first employed to design the speed controller of each wheel for integrating with the Ackermann-Jeantand model-based electronic differential. A model reference adaptive-proportional-integral-derivative control is designed to manipulate the vehicle steering system. The experimental results show that the proposed adaptive functional approximation control and model reference adaptive-proportional-integral-derivative controllers can effectively monitor the wheel rotational speed and steering angle with rotational speed error and angular error less than 2r/min and 0.03 degrees, respectively. The induced electronic differential model successfully assisted the vehicle turning control and trajectory following control operations.
An electronic system for the real-time denoising of fluoroscopic images is proposed in this paper. Fluoroscopic devices use X-rays to obtain real-time moving images of patients and support many surgical interventions ...
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An electronic system for the real-time denoising of fluoroscopic images is proposed in this paper. Fluoroscopic devices use X-rays to obtain real-time moving images of patients and support many surgical interventions and a variety of diagnostic procedures. In order to avoid risks for the patient, X-ray intensity has to be kept acceptably low during the clinical applications. This implies that fluoroscopic images are corrupted by large quantum noise (Poisson-distributed). Real-time noise reduction can offer a better visual perception to doctors and possible further reductions of the dose. The proposed circuit implements a spatio-temporal filter optimized for the removal of the quantum noise while preserving video edges and the prompt response of the image to the introduction of new features in the field. The filter incorporates information on the dependence of the standard deviation of the noise on the local brightness of the image and performs a conditioned average operation. The proposed circuit is implemented on FPGA (field programmable gate array) device allowing the real time elaboration of video streams composed by frames with 1024 x 1024 pixel and uses an external DDR2 (Double Data Rate 2) memory for the storage and the reuse of the fluoroscopic frames needed by the filter. When implemented on StratixIV-GX70 FPGA the circuit is able to process up to 49 fps (frames per second) while using 80% of the logic resources of the FPGA. (C) 2014 Elsevier B.V. All rights reserved.
Solder joint resistance monitoring is important for electronic system prognostics and system health management. It is noted that the typical built-in self-test method of field programmable gate array (FPGA) solder joi...
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Solder joint resistance monitoring is important for electronic system prognostics and system health management. It is noted that the typical built-in self-test method of field programmable gate array (FPGA) solder joint based on charging and discharging of single capacitance has two main shortcomings of large power consumption and unavailability of the monitored pins in FPGA's functional design. In order to overcome these drawbacks, we propose an online measure method of FPGA solder joint resistance with the constraints of limited pin number and low power consumption in this paper. The model of our method is presented in detail, including external test circuit, internal test IP core and parameter determination. The validity of our proposal with low power consumption is upheld by theoretical studies. Furthermore, the corresponding platform of the novel method is built based on a Xilinx Spartan 6 FPGA, and the relative experiments are conducted. Meanwhile, the experiment results show that the method can be used to online measure the resistance of the solder joint of FPGA with lower power consumption than the typical built-in self-test method. (C) 2015 Elsevier Ltd. All rights reserved.
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