A small-scale electric model vehicle is built with four in-wheel motors. A field programmable gate array is chosen as the control kernel for this electric vehicle system. Since this electric model vehicle has four in-...
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A small-scale electric model vehicle is built with four in-wheel motors. A field programmable gate array is chosen as the control kernel for this electric vehicle system. Since this electric model vehicle has four in-wheel driving motors without differential mechanism, it needs an electronic differential and well-designed control algorithm to manipulate the vehicle driving speed and orientation. Accurate mathematical model of this multi-input and multi-output electric vehicle system is difficult to establish for a model-based controller design. Here, the adaptive functional approximation control scheme is first employed to design the speed controller of each wheel for integrating with the Ackermann-Jeantand model-based electronic differential. A model reference adaptive-proportional-integral-derivative control is designed to manipulate the vehicle steering system. The experimental results show that the proposed adaptive functional approximation control and model reference adaptive-proportional-integral-derivative controllers can effectively monitor the wheel rotational speed and steering angle with rotational speed error and angular error less than 2r/min and 0.03 degrees, respectively. The induced electronic differential model successfully assisted the vehicle turning control and trajectory following control operations.
An electronic system for the real-time denoising of fluoroscopic images is proposed in this paper. Fluoroscopic devices use X-rays to obtain real-time moving images of patients and support many surgical interventions ...
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An electronic system for the real-time denoising of fluoroscopic images is proposed in this paper. Fluoroscopic devices use X-rays to obtain real-time moving images of patients and support many surgical interventions and a variety of diagnostic procedures. In order to avoid risks for the patient, X-ray intensity has to be kept acceptably low during the clinical applications. This implies that fluoroscopic images are corrupted by large quantum noise (Poisson-distributed). Real-time noise reduction can offer a better visual perception to doctors and possible further reductions of the dose. The proposed circuit implements a spatio-temporal filter optimized for the removal of the quantum noise while preserving video edges and the prompt response of the image to the introduction of new features in the field. The filter incorporates information on the dependence of the standard deviation of the noise on the local brightness of the image and performs a conditioned average operation. The proposed circuit is implemented on FPGA (field programmable gate array) device allowing the real time elaboration of video streams composed by frames with 1024 x 1024 pixel and uses an external DDR2 (Double Data Rate 2) memory for the storage and the reuse of the fluoroscopic frames needed by the filter. When implemented on StratixIV-GX70 FPGA the circuit is able to process up to 49 fps (frames per second) while using 80% of the logic resources of the FPGA. (C) 2014 Elsevier B.V. All rights reserved.
Solder joint resistance monitoring is important for electronic system prognostics and system health management. It is noted that the typical built-in self-test method of field programmable gate array (FPGA) solder joi...
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Solder joint resistance monitoring is important for electronic system prognostics and system health management. It is noted that the typical built-in self-test method of field programmable gate array (FPGA) solder joint based on charging and discharging of single capacitance has two main shortcomings of large power consumption and unavailability of the monitored pins in FPGA's functional design. In order to overcome these drawbacks, we propose an online measure method of FPGA solder joint resistance with the constraints of limited pin number and low power consumption in this paper. The model of our method is presented in detail, including external test circuit, internal test IP core and parameter determination. The validity of our proposal with low power consumption is upheld by theoretical studies. Furthermore, the corresponding platform of the novel method is built based on a Xilinx Spartan 6 FPGA, and the relative experiments are conducted. Meanwhile, the experiment results show that the method can be used to online measure the resistance of the solder joint of FPGA with lower power consumption than the typical built-in self-test method. (C) 2015 Elsevier Ltd. All rights reserved.
In order to achieve more effective monitoring and to solve the heavy workload issues of installation and removal on the existing wired-system logging site, thus guarantee the safety in normal operation, a wireless log...
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In order to achieve more effective monitoring and to solve the heavy workload issues of installation and removal on the existing wired-system logging site, thus guarantee the safety in normal operation, a wireless logging instrument system is designed to monitor the oil drilling platform. This paper introduces the overall architecture of the wireless system, and develops the hardware system-in which embedded software is designed-based on analog-digital conversion device, field-programmablegatearray chip, and microprocessor. Combined with wireless sensor technology, analog measurements, and encoding quadruple frequency and phase-detection techniques, the wireless nodes in the system can detect and preprocess analog signals in the frequency range from 0.1 to 200 Hz and encoder signals of 90 degrees phase difference, then output data through wireless transmitter module to upper monitoring center. Experimental results show that this system can realize a real-time wireless communication and monitoring for oil drilling platform stably. Moreover, it has features such as coding flexibility, high precision, good reliability, high integration, small size, and low-power consumption. Thus, the system provides a promising solution of data collection and analysis for the drilling platform.
Distributed data acquisition and control systems in large-scale scientific experiments, like e.g. ITER, require time synchronization with nanosecond precision. A protocol commonly used for that purpose is the Precise ...
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Distributed data acquisition and control systems in large-scale scientific experiments, like e.g. ITER, require time synchronization with nanosecond precision. A protocol commonly used for that purpose is the Precise Timing Protocol (PTP), also known as IEEE 1588 standard. It uses the standard Ethernet signalling and protocols and allows obtaining timing accuracy of the order of tens of nanoseconds. The MTCA. 4 is gradually becoming the platform of choice for building such systems. Currently there is no commercially available implementation of the PTP receiver on that platform. In this paper, we present a module in the MTCA. 4 form factor supporting this standard. The module may be used as a timing receiver providing reference clocks in an MTCA. 4 chassis, generating a Pulse Per Second (PPS) signal and allowing generation of triggers and timestamping of events on 8 configurable backplane lines and two front panel connectors. The module is based on the Xilinx Spartan 6 FPGA and thermally stabilized Voltage Controlled Oscillator controlled by the digital-to-analog converter. The board supports standalone operation, without the support from the host operating system, as the entire control algorithm is run on a Microblaze CPU implemented in the FPGA. The software support for the card includes the low-level API in the form of Linux driver, user-mode library, high-level API: ITER Nominal Device Support and EPICS IOC. The device has been tested in the ITER timing distribution network (TCN) with three cascaded PTP-enabled Hirschmann switches and a GPS reference clock source. An RMS synchronization accuracy, measured by direct comparison of the PPS signals, better than 20 ns has been obtained.
This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi-core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes u...
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This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi-core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data-mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time.
Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the r...
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Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the radial polynomials used to define them and the large inverse matrix calculation needed for the linear fit. This paper presents an efficient parallel method for calculating Zernike coefficients from phase gradients produced by a Shack-Hartman sensor and its real-time implementation using an FPGA by pre-calculation and storage of subsections of the large inverse matrix. The architecture exploits symmetries within the Zernike modes to achieve a significant reduction in memory requirements and a speed-up of 2.9 when compared to published results utilising a 2D-FFT method for a grid size of 8 x 8. Analysis of processor element internal word length requirements show that 24-bit precision in precalculated values of the Zernike mode partial derivatives ensures less than 0.5% error per Zernike coefficient and an overall error of < 1%. The design has been synthesized on a Xilinx Spartan-6 XC6SLX45 FPGA. The resource utilisation on this device is < 3% of slice registers, < 15% of slice LUTs, and approximately 48% of available DSP blocks independent of the Shack-Hartmann grid size. Block RAM usage is < 16% for Shack-Hartmann grid sizes up to 32 x 32.
Radiation-induced multiple bit upsets (MBUs) degrade the reliability of scaled static random access memory (SRAM)-based field programmable gate arrays (FPGAs). Reducing the correction time for MBU and preventing the e...
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Radiation-induced multiple bit upsets (MBUs) degrade the reliability of scaled static random access memory (SRAM)-based field programmable gate arrays (FPGAs). Reducing the correction time for MBU and preventing the error accumulation are the challenges faced by error correction code (ECC) integrated FPGAs. In this paper, a novel built-in ECC using encode-and-compare of the data and parity bits is proposed to reduce the correction time and improve the reliability of FPGA. Implementation has been carried out in FPGA to confirm its effectiveness. The proposed method is 5 times faster than existing CRC based inbuilt error mitigation solution. This work opens a door for 2-D ECC to be universally used in FPGAs for safety-critical applications. (C) 2015 Elsevier Ltd. All rights reserved.
Nowadays the weak signal detection technology is necessary in scientific research field, in which the phase-locked amplifying technology is widely used in the field of weak signal detection because it can meet the req...
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Nowadays the weak signal detection technology is necessary in scientific research field, in which the phase-locked amplifying technology is widely used in the field of weak signal detection because it can meet the requirements of high speed and high *** Generator software is adopted as a tool since System Generator can make the design more conveniently and *** design of each module in orthogonal vector type digital phase-locked amplifier is introduced in this *** overall design was *** simulation results confirm that the design is feasible.
Centralized and multilevel implementations of the Panoptic omnidirectional multiaperture visual system were previously presented by us, relying on the transmission of all camera outputs to a single central processing ...
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Centralized and multilevel implementations of the Panoptic omnidirectional multiaperture visual system were previously presented by us, relying on the transmission of all camera outputs to a single central processing node for omnidirectional image and video reconstruction. In this paper, a novel distributed and parallel implementation of the omnidirectional vision reconstruction algorithm of the Panoptic system is presented. The parallel approach aims to overcome the scalability problems and memory bandwidth limitations of the centralized approach. The real-time hardware implementation is presented for camera modules with image processing, memory, and interconnectivity features. A methodology is introduced for the arrangement of camera modules with interconnectivity feature into a target interconnection network topology. A unique custom-made multiple-field-programmablegatearray hardware platform is introduced for the implementation of an interconnected network of 49 camera prototype Panoptic system. A hardware architecture based on presented hardware platform enabling the real-time implementation of the blending algorithms is presented, along with the imaging results and resource utilization. The real-time implementation results of the implemented omnivision application on the mentioned prototype are demonstrated.
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