In this paper, the use of the Dual Kalman Filter for the identification of photovoltaic system parameters is presented. The system includes the photovoltaic source, the dc/dc converter and the battery/dc bus and both ...
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In this paper, the use of the Dual Kalman Filter for the identification of photovoltaic system parameters is presented. The system includes the photovoltaic source, the dc/dc converter and the battery/dc bus and both its states and parameters in the actual operating conditions are identified. In particular, the proposed approach gives the confidence interval for the system settling time, which is used for the real-time optimization of the perturbative maximum power point tracking algorithm. The proposed technique is implemented by using a field-programmablegatearray and it is validated by means of both simulation and experimental results.
In today's technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate ...
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In today's technological era, SOC has undergone rapid evolution and is still processing at a swift pace. But due to this explosive evolution of semiconductor industry, the devices are scaling down at a rapid rate and hence, SOC today have become communication-centric. However, the existing bus architectures comprising of wires for global interconnection in SOC design are undergoing design crises as they are not able to keep up with the rate of scaling down of devices. To overcome bottleneck of communication system, NOC is an upcoming archetype. In on-chip network, router is considered as an important component. This paper proposes router, its components and parameters which affects the entire design. Thus, to validate the functioning of NOC on hardware, router has been designed in VHDL and simulated in Xilinx ISE 14.1 targeting Xilinx XC5VLX30-3 FPGA.
Quantum key distribution (QKD) is a newly developed technique to assign physically and absolutely secure bits between two communication sides. This makes the one-time-pad encryption possible and thus provides theoreti...
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Quantum key distribution (QKD) is a newly developed technique to assign physically and absolutely secure bits between two communication sides. This makes the one-time-pad encryption possible and thus provides theoretical security for cryptology. The authentication is an indispensable process in the QKD. A high speed QKD system requires an expeditious realization of authentication. We develop an authentication computation core based on field programmable gate array (FPGA) which can reach the throughput of 4.8 Gbps and 1.6 Gbps. A detailed protocol to guarantee the functionality of the authentication computation core is also proposed. (C) 2015 Elsevier GmbH. All rights reserved.
Fast evolution of high-performance cameras in recent years has made them promising tools for observing transient and fast events in large-scale scientific experiments. Complex experiments, such as ITER, take advantage...
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Fast evolution of high-performance cameras in recent years has made them promising tools for observing transient and fast events in large-scale scientific experiments. Complex experiments, such as ITER, take advantage of high-performance imaging system consisting of several fast cameras working in the range of visible and infrared light. However, the application of such devices requires a usage of high-performance data acquisition systems able to read and transfer large amount of data, reaching even 10 Gbit/s for a single camera. The MTCA.4 form factor fulfils the requirements of demanding imaging systems. The paper presents a first implementation of a complete image acquisition system built on the basis of MTCA.4 architecture, which is dedicated for the operation with high-resolution fast cameras equipped with Camera Link interface. Image data from the camera are received by the frame grabber card and transmitted to the host via the PCIe interface. The modular structure of MTCA.4 architecture allows connecting several cameras to a single MTCA chassis. The system can operate in two modes: with internal CPU installed in the MTCA chassis or with external CPU connected to the chassis with PCIe link. The usage of the external CPU opens a possibility to aggregate data from different subsystems. The system supports precise synchronization with the time reference using Precise Timing Protocol (IEEE 1588). The timing modules ensure clock distribution and triggers generation on backplane lines. These allow synchronization of image acquisition from different cameras with high precision. The software support for the system includes low-level drivers and API libraries for all components and a high-level EPICS-based environment for system control and monitoring.
Semaphore is a kind of mechanism used in a multithreaded environment to ensure that two or more key code segments are not concurrently invoked. In order to enhance the response capability of real-time operating system...
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Semaphore is a kind of mechanism used in a multithreaded environment to ensure that two or more key code segments are not concurrently invoked. In order to enhance the response capability of real-time operating systems, a hardware design scheme to implement semaphore management based on field programmable gate array is put forward in this paper. We take the mu C/OS-II real-time operating system as an example to design hardware logical circuits of semaphore management function module according to its parallel characteristics, and simulation tests under Xilinx ISE software environment are performed. The simulation results show that implementing semaphore management by hardware can obviously improve the execution time of creating/deleting a semaphore, applying for/releasing a semaphore and P/V operations;therefore, the whole reliability of the real-time operating system is greatly improved.
Low-cost high-quality electrocardiographic diagnosis systems, Body Area Sensor Networks (BASNs) have become important for healthcare service providers but security and integrity of medical signal are not widely resear...
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Low-cost high-quality electrocardiographic diagnosis systems, Body Area Sensor Networks (BASNs) have become important for healthcare service providers but security and integrity of medical signal are not widely researched. This paper proposes a simple and novel partial encryption for the security of electrocardiographic data. The scheme is designed and developed on a configurable FPGA device and uses only half of the ECG data for encryption. Since the computation is done on reduced data, the computation cost is decreased and the processing speed of encryption process is augmented. The proposed hardware was implemented on Xilinx Virtex4 and Spartan3 FPGA giving maximum clock frequency of 286.8 MHz and 139.5 MHz respectively. The encrypted data along with the remaining unencrypted part of the data are used to construct the encrypted electrocardiographic signal giving it a noise like characteristics. This makes the encrypted signals uncorrelated to original ECG giving an average cross-correlation of -0.00024.
A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded ...
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A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented using a field-programmablegatearray. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.
Solar power is the major renewable energy source opted by developing countries as stand-alone / Grid enabled system. Industries and educational institutions are opting for solar energy to combat power crisis. This pap...
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Solar power is the major renewable energy source opted by developing countries as stand-alone / Grid enabled system. Industries and educational institutions are opting for solar energy to combat power crisis. This paper proposes knowledge based, self configurable, smart controller to efficiently use solar energy according to load, under frequent grid failure environment. It is enabled with fault identification and isolation. Extension to higher power capacity is easily achieved with plug and play mechanism. Proposed control architecture is implemented using field programmable gate array (FPGA), that supports modular level implementation with well defined interfaces for each sub-system. It can be used with low power as well as high power photo-voltaic system. Efficiency of the proposed architecture is demonstrated for the photo-voltaic system installed in educational institution.
The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slic...
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The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slices, DSP48, block random access memory, computation time, latency and power consumption are presented. An improved design of a loosely coupled GPS/INS integrated system is described in this paper. The inertial navigation solution and Kalman filter computations are provided by the MicroBlaze on Virtex-6 FPGA. The real time processed navigation solutions are updated with a rate of 100 Hz.
The objective of the paper is to develop soft switching for the novel five level full bridge DC-DC converter for high power applications. The use of conventional DC-DC converter is likely to decrease the efficiency be...
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The objective of the paper is to develop soft switching for the novel five level full bridge DC-DC converter for high power applications. The use of conventional DC-DC converter is likely to decrease the efficiency because of the hard switching, which generates losses during the switch on/off. This paper mainly deals with the development of zero voltage and zero current switching for five level full bridge DC-DC converter. The proposed topology will provide five level DC-DC output voltage, thereby the size of filter in both input and out sides will get reduced as compared to the existing topologies. By increasing the voltage levels, the stress across each switch and DC filter in the rectifier side will get reduced. Only eight switches are used for generating five levels in the proposed converter topology which reduces cost and also total switching losses, thus improves the overall efficiency of a system and it is very much suitable for high power DC-DC applications. The control signals for the proposed converter are developed from the field programmable gate array. The simulation and experimental results are presented for prototype model of 500 W.
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