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IEEE International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)

作者： Ramesh, S. Seshasayanan, R. Sathyabama Univ Madras Tamil Nadu India Anna Univ Dept ECE Madras Tamil Nadu India

ISBN: (纸本)9781467398251

In order to increase the quality of the real time application it is essential to improve the throughput, capability of the network in new generation of WLAN. In recent days, the wide local area networks are combined with MIMO and OFDM wireless technologies. It is well known that OFDM provides a high data rate with low complexity. The robustness of the OFDM provides high data rates. It comprises multiplexing in modulations, so that OFDM can able to increase the interference of the channel. In this paper is focused to improve the quality of service on 802.11n standard MIMO-OFDM wireless systems. To do this, a new extended-OFDM transceiver is designed by modifying the modulation, encoding-decoding and FFT techniques by applying QAM, Optimum Frequency domain response encoding and 64 lines FFT with Radix4 Decimation in Time (DIT) by prime factor algorithm respectively. The main unit of OFDM is FFT. Optimizing FFT requires high attention. Hence by generalizing FFT algorithm the performance of the system is improved in terms of high throughput and low complexity. The simulation results shows that the proposed transceiver is efficient than the existing system.

关键词： Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing Spatial Multiplexing Space Time Block Code field programmable gate array Wireless Communication

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Rotator on Chip (RoC) design based on ring topological NoC 1

Rotator on Chip (RoC) design based on ring topological NoC

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International Conference on Advanced Computing Technologies and Applications (ICACTA)

作者： Kumar, Adesh Baruah, Lopamudra Sabu, Amit Univ Petr & Energy Studies Dept Elect & Instrumentat Engn Dehra Dun India

The paper presents the ring based Network on Chip (NoC) structure design and modeling in Hardware Description Language (HDL). The network configuration is chosen for 65536 nodes, which is synchronized with same clock pulse. The functionality of each node is checked in Modelsim 10.1b software. The interprocess communication among nodes in verified using Virtex-5 FPGA. The priority of the nodes is assigned using FIFO logic, which is integrated with the NoC chip. The NoC architecture is based on token ring based network concept, called Rotator-on Chip (RoC). The design and modeling is done in Xilinx 14.2 ISE using VHDL programming language and synthesized on Digilent manufactured FPGA, with the target device, xc5vlx20t-2-ff323, Virtex-5. Hardware and timing parameters are extracted from the synthesized results and maximum frequency is found 535.733MHz and memory utilization is 263208 kB. (C) 2015 The Authors. Published by Elsevier B.V.

关键词： Rotator on Chip Network on Chip Hardware Description Language Very large Scale of Integration field programmable gate array

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Evaluation of FSO Link Throughput in Qatar 4

Evaluation of FSO Link Throughput in Qatar

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4th Mediterranean Conference on Embedded Computing (MECO

作者： Hussain, Syed Jawad Touati, Abir Elamri, Mohamed Touati, Farid Uysal, Murat Qatar Univ Dept Elect Engn Doha Qatar

ISBN: (纸本)9781479989997

Despite the vibrant advantages of Free Space Optics (FSO) technology and the variety of its applications, its widespread adoption has been hampered by rather disappointing link reliability for long-range links due to atmospheric turbulence-induced fading and sensitivity to detrimental climate conditions. A major challenge of such hybrid systems is to provide a strong backup system with soft-switching capabilities when the FSO link becomes down. The specific objective of this work is to study for the first time in Qatar and the Gulf Cooperation Council (GCC) the link capacity, link availability, and link outage of an FSO system with Radio Frequency (RF) back up (i.e. hybrid FSO/RF). In order to analyze the two transport media, we have designed a network sniffer application in Linux and embedded it in FPGA. We have installed new FSO/RF terminals and configure and align them successively. In the reporting period, we carry out measurements and relate them to real-time weather conditions. The relative humidity, which is due to high temperature and does not generally form fogs, was found to be the main factor degrading the FSO link throughput rather than the fog as reported in previous studies in Europe and North America.

关键词： Free Space Optics Radio Frequency field programmable gate array Embedded Development kit (EDK)

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Hardware Implementation of MFCC-Based Feature Extraction for Speaker Recognition 1

Hardware Implementation of MFCC-Based Feature Extraction for...

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1st International Conference on Communication and Computer Engineering (ICOCOE)

作者： Ehkan, P. Zakaria, F. F. Warip, M. N. M. Sauli, Z. Elshaikh, M. Univ Malaysia Perlis Sch Comp & Commun Engn Arau 02600 Perlis Malaysia Univ Malaysia Perlis Sch Microelect Engn Arau 02600 Perlis Malaysia

ISBN: (纸本)9783319076744;9783319076737

The most important issues in the field of speech recognition and representative of the speech is a feature extraction. Feature extraction based Mel Frequency Cepstral Coefficient (MFCC) is one the most important features required among various kinds of speech application. In this paper, FPGA-based for speech features extraction MFCC algorithm is proposed. The complexities of computational as well as the requirement of memory usage are characterized, analyzed, and improved. Look-up table (LUT) scheme is used to deal with the elementary function value in the MFCC algorithm and fixed-point arithmetic is implemented to reduce the cost under accuracy study. The final feature extraction design is implemented effectively into the FPGA-Xilinx Virtex2 XC2V6000 FF1157-4 chip.

关键词： Speaker recognition Mel frequency cepstral coefficients field programmable gate array

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field programmable gate array-Based Attitude Stabilization

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JOURNAL OF AEROSPACE COMPUTING INFORMATION AND COMMUNICATION 2009年第7期6卷 451-463页

作者： Stepaniak, Michael J. de Haag, Maarten Uijt van Graas, Frank USAF Inst Technol Dept Elect & Comp Engn Wright Patterson AFB OH 45433 USA Ohio Univ Avion Engn Ctr Stocker Ctr 321B Athens OH 45701 USA

A system for determining vehicle attitude using a field programmable gate array and low-cost gyroscopes is presented. The method is intended to support the stabilization of a short duration, unmanned aerial vehicle. Using a microelectromechanical system inertial sensor for the calibration and serial interface, the algorithm sidesteps concerns related to electromagnetic interference and the impact of embedded, proprietary filters. An Allan variance analysis is used to characterize the sensor errors and predict system performance. A floating point representation using a direction cosine matrix is hosted on the field programmable gate array alongside the platform stabilization feedback loops. Although prone to drifting without additional aiding, the derived attitude has been demonstrated to be effective in stabilizing a remotely piloted quadrotor.

关键词： field programmable gate array Inertial Sensor Quadrotor Gyroscopes Microelectromechanical Systems Electromagnetic Interference Micro Air Vehicle Feedback Loop Attitude Stabilization Flight Testing

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Multi-FPGA Implementation of Feedforward Network and its Performance Analysis 34

Multi-FPGA Implementation of Feedforward Network and its Per...

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34th Chinese Control Conference (CCC)

作者： Wang, Jiang Yang, Shuangming Deng, Bin Wei, Xile Yu, Haitao Tianjin Univ Sch Elect Engn & Automat Tianjin 300072 Peoples R China

ISBN: (纸本)9789881563897

Multi-FPGA system for the design of the spiking neural network is a great challenge for hardware acceleration. Multilayer feedforward neural networks (FNNs) are vitally important for the study of the coding problems in sensory organs. In this paper a multilayer FNN is implemented on a multi-FPGA-based system, which can guarantee both the high computational efficiency and the large network scale. The time-division multiplexing technology is employed in the proposed platform to be cost-efficient. In addition, since a parallel structure is used in the hardware design, the proposed hardware implementation can speedup approximately 4.8x10(4) times faster than the real-world biological behaviors in a high computational precision. Clock synchronization is considered in the design of the FNN to guarantee the accuracy of the signal transmission between layers. The proposed system can be applied to a broad kinds of fields such as the control of motors and the artificial intelligence, and the presented neurons can be replaced by more complicated neurons for the study of other dynamical characteristics of the neural networks.

关键词： Feedforward network field programmable gate array multi-chip system real time

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Data Aggregation in Wireless Sensor Networks for Lunar Exploration 6

Data Aggregation in Wireless Sensor Networks for Lunar Explo...

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6th International Conference on Emerging Security Technologies (EST)

作者： Zhai, Xiaojun Vladimirova, Tanya Univ Leicester Dept Engn Leicester Leics England

ISBN: (纸本)9781467397995

This paper presents research work related to the development of Wireless Sensor Networks (WSN) gathering environmental data from the surface of the Moon. Data aggregation algorithms are applied to reduce the amount of the multi-sensor data collected by the WSN, which are to be sent to a Moon orbiter and later to Earth. A particular issue that is of utmost importance to space applications is energy efficiency and a main goal of the research is to optimise the algorithm design so that the WSN energy consumption is reduced. An extensive simulation experiment is carried out, which confirms that the use of the proposed algorithms enhances significantly the network performance in terms of energy consumption compared to routing the raw data. In addition, the proposed data aggregation algorithms are implemented successfully on a System-on-a-chip (SoC) embedded platform using a Xilinx Zynq FPGA device. The data aggregation has two important effects: the WSN life time is extended due to the saved energy and the original data accuracy is preserved. This research could be beneficial for a number of future security related applications, such as monitoring of phenomena that may affect Earth's planetary security/safety as well as monitoring the implementation of Moon treaties preventing establishment of military bases on the lunar surface.

关键词： Wireless Sensor Network Sensor Data Aggregation Planetary Exploration field programmable gate array

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Improved Controlled Start-up Stochastic LDPC Decoder for Efficient FPGA-based Implementation 4

Improved Controlled Start-up Stochastic LDPC Decoder for Eff...

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2015 4th International Conference on Electrical Engineering (ICEE)

作者： Zerari, Ghania Guessoum, Abderrezak Univ Blida LATSI Lab Dept Elect Blida Algeria

ISBN: (纸本)9781467366731

This paper introduces a new and an improved controlled start-up stochastic (CSS) architecture of Low-Density Parity- Check (LDPC) decoding, to implement fully parallel FPGA-based decoders. The developed architecture uses a new variable nodes structure with larger internal memory lengths, to improve the convergence, without significant additional field programmable gate array (FPGA) resource. To validate the advantage of the proposed approach, a medium (1024, 512) and short (200, 100) codes are implemented. The results of Xilinx Virtex-6 VLX240T FPGA shoes that the variable node internal memories lengths can be increased from 2-bit, used in CSS and Delayed Stochastic (DS) decoders, to 64-bit without addition resource.

关键词： improved controlled start-up stochastic decoding stochastic decoding low-density parity-check code field programmable gate array

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C-GEP: Platform Demo for 100 Gbit/s Network Monitoring 14

C-GEP: Platform Demo for 100 Gbit/s Network Monitoring

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IFIP/IEEE International Symposium on Integrated Network Management (IM)

作者： Tothfalusi, Tamas Orosz, Peter Varga, Pal Univ Debrecen Fac Informat Debrecen Hungary Budapest Univ Technol & Econ Dept Telecommun & Media Informat Budapest Hungary

ISBN: (纸本)9783901882760

As the line rate reaches and exceeds 100 Gbit/s, the usage of hardware-accelerated networking equipment is getting a natural choice when evaluating newly developed network-related features. The requirement for high throughput and high level of reconfiguration together put field programmable gate array (FPGA) technology into the focus of high performance networking. In this demonstration, we show some of the capabilities of a new, 100 Gigabit Ethernet Evaluation Platform, called C-GEP. Since the hardware is reconfigurable, the platform can host a wide range of high-speed network specific applications, and it is aligned with the Software Defined Networking (SDN) principles. Our demonstration contains two different implementations of 100 Gbit/s-capable applications: a traffic generator and a traffic monitor engine. Our aim here is to show the feasibility of C-GEP for high-speed networking evaluations.

关键词： network management network monitoring 100 Gbit/s Ethernet traffic analysis reconfigurable hardware field programmable gate array

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Efficient IIR Notch Filter Design using Minimax Optimization for 50Hz Noise Suppression in ECG

Efficient IIR Notch Filter Design using Minimax Optimization...

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International Conference on Signal Processing, Computing and Control (ISPCC)

作者： Jayant, Hemang K. Rana, K. P. S. Kumar, Vineet Nair, Sreejith S. Mishra, Puneet Netaji Subhas Inst Technol Instrumentat & Control Engn Dept Sect 3 New Delhi 110078 India

ISBN: (纸本)9781479984367

Quality of Electrocardiogram (ECG) signal is very important for patient health diagnostics. ECG consists of frequencies ranging from 0.01 - 300Hz, while being a very small magnitude signal. ECG usually gets corrupted by the 50Hz power line interference (PLI). Thus, filtering out the PLI is a necessary task for the right diagnostics. In this work a second order efficient digital infinite impulse response (IIR) notch filter is designed to suppress PLI. For this task, Minimax optimization technique has been utilized to minimize the root mean square error (RMSE) defined as the difference of magnitude response of ideal and proposed IIR notch filter designs. The optimization process was able to set pole position close to the unit circle and the pass band gain is so chosen so as to have symmetrical performance resulting in attenuation at 50Hz notch of -260dB, a gain of 0.995 and -3dB bandwidth of 2.375Hz. The performance of the designed filter has been investigated theoretically as well as validated experimentally on a contaminated ECG signal and a pure sinusoid signal of 50Hz on field programmable gate array (FPGA) in the LabVIEW environment. In simulation, a power spectral density (PSD) of -30dB has been achieved for the simulated ECG signal originally having 4dB PSD at 50Hz and an attenuation of -30dB in PSD has been obtained for a pure sinusoidal signal. The designed filter was also implemented on FPGA a PSD of -26dB was obtained for ECG at 50Hz and -26dB for sinusoidal signal, respectively. Based on these studies it can be concluded that the proposed Minimax based notch filter design is an efficient one.

关键词： notch filter infinite impulse response ECG signal field programmable gate array minimax power line noise suppression

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