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51st Annual IEEE AUTOTESTCON Conference

作者： Nunn, Chris Natl Instruments High Speed Serial Test Austin TX USA

ISBN: (纸本)9781479981908

Technology is trending towards more data, faster rates, smaller size, and less power. Better performance with a reduced footprint is hard to accomplish, but about 10 years ago, engineers solved this challenge for data movement by moving to a different digital communication paradigm. Instead of the traditional parallel buses that transmit clock and data separately, high-speed serial technology emerged that allows transmission of encoded data without the need for a separate clock signal. This has allowed industry to break the 1-2 GHz practical limit inherent to parallel busses and reach speeds over 50 GHz. This brings new challenges to test engineers and the systems they develop. For one, typical test equipment to monitor signals transitioning in the GHz ranges is expensive. Secondly, there are multiple layers of a communication link that need to be tested, which typically requires different instruments for different layers. Finally, many industries such as Aerospace and Defense choose to use custom protocols for security, efficiency, or redundancy, which make it harder to use COTS (Commercial Off-The-Shelf) protocol layer test solutions. Using test equipment with FPGAs (field-programmable gate arrays) can help combat these challenges. For example, FPGA manufacturers have invested significant resources into developing tools that give insight into physical link margin analysis. These tools allow users to view eye diagrams that look similar to what you would traditionally view on an oscilloscope, for a fraction of the cost. Furthermore, full protocol stacks can be implemented on the FPGAs, allowing protocol aware test equipment that can make decisions in real-time. In addition, if the FPGA on that test equipment is user programmable, engineers can implement their custom protocol on the FPGA for custom protocol functional test solutions. User programmable FPGAs also improve obsolescence management by allowing users to emulate obsolete parts through programming the obsole

关键词： FPGA field programmable gate array Cost of Test BERT Oscilloscope High-Speed Serial Protocol SERDES COTS Obsolescence Management

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The FPGA Design of JPEG-LS Image Lossless Decompression IP Core

The FPGA Design of JPEG-LS Image Lossless Decompression IP C...

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Chinese Automation Congress (CAC)

作者： Deng, Lihua Huang, Zhenghua Huazhong Univ Sci & Technol Inst Pattern Recognit & Artificial Intelligence Wuhan Peoples R China Three Gorges Univ Coll Comp & Informat Technol Yichang Peoples R China

ISBN: (纸本)9781467371896

This paper presents the key optimization techniques for an efficient accelerator implementation in an image decoder IP core design for real-time Joint Photographic Experts Group Lossless (JPEG-LS) decoding. Pipeline architecture, frequency multiplication technique and accelerator elements have been utilized to enhance the throughput capability. Improved parameters mapping schemes have been adopted for the purpose of low complexity and small chip die area. It has been proved that these hardware-oriented optimization techniques make the decoder meet the requirements of the IP core implementation. The proposed optimization techniques have been verified in the implementation of the JPEG-LS decoder IP, and then validated in a real satellite image receiving system.

关键词： Joint Photographic Experts Group Lossless field programmable gate array Intellectual Property core pipeline line

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Embedded Synthetic Instruments for O-Level Test Modular IO and FPGA Technology Provide Increased Flexibility and Decreased Cost of Test 51

Embedded Synthetic Instruments for O-Level Test Modular IO a...

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51st Annual IEEE AUTOTESTCON Conference

作者： Bauer, Robert Natl Instruments Modular Instruments Austin TX USA

ISBN: (纸本)9781479981908

System complexity in the aerospace, defense, and automotive industries continues to increase. This puts demand on test engineers to produce novel solutions that decrease the cost of testing system components. Moving forward, these engineers will be faced with the difficulties of maintaining an increasing volume of legacy hardware while simultaneously developing solutions to test new technologies. Software-designed synthetic instruments are a fairly new way of tackling this challenge, however this technology has mainly been applied to larger, depot and intermediate level testers. Recent developments in the embedded market offer a promising way to apply this technology to organizational level test. By focusing on the optimization of size, weight, and power, engineers are beginning to package instrument grade IO and powerful FPGAs into COTS solutions optimized for deployment. Furthermore, advances in the programming experience for FPGAs are enabling software engineers to program FPGAs using high-level text based and graphical programming languages. While these technologies are being driven mainly by embedded systems designers, they are well suited to address the challenges facing O-level test. The combination of modular IO, FPGAs, and embedded processors is differentiated in three primary ways: physical layer interchangeability, protocol layer flexibility, and the ability to easily correlate measurements made in the field with those in the factory. When built with modular IO, a tester can be easily reconfigured to interface with a number of different components. Given the right adapter, most digital signals including single ended, differential, serial, and high speed serial signals can be brought directly to the FPGA for processing. Once on the FPGA, signals are typically brought into a user-defined protocol layer for protocol aware test, greatly decreasing test time over conventional post-processing methods. The level of customization supported by implementing the pro

关键词： FPGA field programmable gate array Organizational Level Test O-level test Synthetic Instrument Protocol COTS

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Towards Ideal Arbiter PUF Design on Xilinx FPGA: a Practitioner's Perspective 18

Towards Ideal Arbiter PUF Design on Xilinx FPGA: a Practitio...

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18th Euromicro Conference on Digital System Design (DSD)

作者： Sahoo, Durga Prasad Chakraborty, Rajat Subhra Mukhopadhyay, Debdeep Indian Inst Technol SEAL CSE Kharagpur 721302 W Bengal India

ISBN: (纸本)9781467380355

Despite the perceived lightweight and structural regularity of Arbiter PUF (APUF), high quality (bias-free) large APUF implementation on FPGA has traditionally proved to be challenging. Currently, the most widely accepted design approach for FPGA-based APUF implementation is the programmable Delay Line (PDL) based APUF. In this work, we describe a scalable design methodology to implement close-to-ideal APUF on Xilinx FPGA using the standard Xilinx CAD tool flow. The main insight is to exploit the Hard Macro feature of the Xilinx design flow to design bias-free symmetric delay paths. We have demonstrated the effectiveness and superiority of our design to previously proposed PDL-based PUFs through implementation and characterization results.

关键词： Arbiter PUF field programmable gate array programmable Delay Line Process Variation

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Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in field programmable gate arrays

Evolutionary Digital Circuit Design with Fast Candidate Solu...

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IEEE International Conference on Evolvable Systems (ICES)

作者： Dobai, Roland Glette, Kyrre Torresen, Jim Sekanina, Lukas Brno Univ Technol Fac Informat Technol CS-61090 Brno Czech Republic Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781479944798

field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches have been developed for effective establishment and evaluation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirm that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time as well as solutions with better quality.

关键词： evolutionary computation field programmable gate arrays integrated circuit design FPGA chromosome configuration frame evolutionary algorithm evolutionary digital circuit design fast candidate solution establishment field programmable gate array granularity level hardware implementation mutation operator Biological cells Digital circuits field programmable gate arrays Sociology Statistics Table lookup Training field programmable gate arrays Feasible Solution evolutionary algorithm digital circuits Table lookup cytology integrated circuit design Sociology Chromosomes Training Functional training

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Structural Modification based Netlist Obfuscation Technique for PLDs

Structural Modification based Netlist Obfuscation Technique ...

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International Conference on Wireless Communications, Signal Processing and Networking

作者： G. Sumathi L. Srivani D. Thirugnana Murthy Anish Kumar K. Madhusoodanan S. A. V. Satya Murty Homi Bhabha National Institute Kalpakkam Tamilnadu-603102 India Indira Gandhi Centre for Atomic Research Kalpakkam Tamilnadu-603102 India

ISBN: (纸本)9781467393393

Logic obfuscation is widely followed in intellectual property cores and chip designs as hardware protection mechanism against design security threats such as reverse engineering (RE), piracy, cloning, overbuilding, etc. In general, sequential obfuscation has two modes of operation such as obfuscated and functional modes. Finite state machines (FSM) are being used to implement the mode control. When a specific sequence of input vectors is applied during power up for user authentication, the circuit will enter into functional mode. Otherwise, FSM remains in obfuscated mode and do not perform the intended functionality. In general, hardware obfuscation technique is applicable to all programmable logic devices. However, we applied the structural modification based netlist obfuscation methodology to field programmable gate array devices. The software implementation of sequential obfuscation is performed for a set of ISCAS'89 benchmark circuits using Libero IDE v9.1 on Actel device. As simulation/structural analysis are the conventional methods to perform RE, we aimed to achieve a high percentage of simulation/structural mismatch during RE. We presented two scenarios of obfuscation: 1) For better structural mismatch during RE, insertion of obfuscation cells at different numbers of high fanout (HF) nets with minimum initialization sequence length (L). As per the designer's area constraint, the total number of nets to be obfuscated is chosen. 2) For better functional simulation mismatch during RE, FSM with different L values is included in the design with a minimum number of obfuscation cells. The initialization sequence length is decided concerning the system clock cycle (i.e. delay constraint). Based on the control signals derived from FSM, the values at HF obfuscated nets are decided. That is, the circuit executes the required functionality only in the functional mode. Hence, the simulation/structural RE complexity of PLDs is improved. This paper discusses the simulation

关键词： field programmable gate array Obfuscation Reverse engineering

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TID Response of Various field programmable gate arrays and Memory Devices

TID Response of Various Field Programmable Gate Arrays and M...

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European Conference on Radiation and its Effects on Components and Systems

作者： J. M. Armani J. L. Leray R. Gaillard V. Iluta CEA LIST Laboratoire de Fiabilite et Integration des Capteurs CEA DIF Consultant on Radiation Effects ERMES Domaine Technologique de Saclay

ISBN: (纸本)9781509002337

The Total Ionizing Dose (TID) tolerance of some FPGAs and memory devices has been evaluated. Two FPGAs and five memories of various types and technologies have been irradiated. Results show that the total dose tolerance of the tested FPGAs is around 200 Gy. The SRAM is the most tolerant device with a failure dose level over 2.4 kGy. Two Flash memories were still well-functioning after 1 kGy.

关键词： CMOS field programmable gate array Flash MRAM SRAM Total Ionizing Dose

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An Efficient FPGA based Real-Time Implementation Shunt Active Power Filter for Current Harmonic Elimination and Reactive Power Compensation

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JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY 2015年第4期10卷 1655-1666页

作者： Charles, S. Vivekanandan, C. Sri Shakthi Inst Engn & Technol Dept Elect & Elect Engn Coimbatore Tamil Nadu India SNS Coll Engn Dept Elect & Elect Engn Coimbatore Tamil Nadu India

This paper proposes a new approach of field programmable gate array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

关键词： Digital control Shunt active power filter field programmable gate array Harmonic elimination Reactive power compensation Synchronous reference frame transformation

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A general-purpose framework for FPGA-accelerated genetic algorithms

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INTERNATIONAL JOURNAL OF BIO-INSPIRED COMPUTATION 2015年第6期7卷 361-375页

作者： Guo, Liucheng Funie, Andreea Ingrid Xie, Zhongliu Thomas, David Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England

FPGA-based genetic algorithms (GAs) can effectively optimise complex applications, but require extensive hardware architecture customisation. To promote these accelerated GAs to potential users without hardware design experience, this study proposes a general-purpose automated framework for creating and executing a GA system on FPGAs. This framework contains scalable and customisable hardware architectures while providing a unified platform for different chromosomes. At compile-time, only a high-level input of the target application needs to be provided, without any hardware-specific code being necessary. At run-time, application inputs and GA parameters can be tuned, without time-consuming recompilation, for finding further good configurations of GA execution. The framework was tested on a high performance FPGA platform using nine problems and benchmarks, including the travelling salesman problem, a locating problem and the NP-hard set covering problem. Experiments show the system's flexibility and an average speedup of 29 times over a multi-core CPU.

关键词： genetic algorithm field programmable gate array FPGA automated framework

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Efficient Audio Filter Using Folded Pipelining Architecture Based on Retiming Using Evolutionary Computation

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2015年第5期24卷

作者： Yagain, Deepa Balla, Sivanag Krishna, Vijaya PES Inst Technol Dept ECE Bangalore 560085 Karnataka India

It is important in digital signal processing (DSP) architectures to minimize the silicon area of the integrated circuits. This can be achieved by reducing the number of functional units such as adders and multipliers. In literature, folding technique is used to reduce the functional units by executing multiple algorithm operations on a single functional unit. Register minimization techniques are used to reduce the number of registers in a folded architecture. Retiming is a technique that needs to be performed before applying folding. In this paper, retiming is performed based on nature inspired evolutionary computation method. This technique generates the database of solutions from which best solution can be picked for folding further. As a part of this work, an efficient folded noise removal audio filter prototype is designed as an application example using evolutionary computation-based retiming and folding with register minimization. Folding technique will however increase the number of registers while multiplexing datapath adder and multiplier elements. Register minimization technique is used after folding to reduce the number of registers. After obtaining retimed, folded filter architecture, low level synthesis is performed which involves mapping of datapath adder and multiplier blocks to actual hardware. Various architectures of adders and multipliers are compared in area-power-performance space and depending on the user defined constraint, folded architecture with specific combination of data path elements is mapped on to hardware. A framework is designed in this paper to automate the entire process which reduces the design cycle time. All the designed filters are targeted for ASIC implementation. The results are compared and are provided as part of simulation results.

关键词： Folding technique retiming area optimization evolutionary computation synthesis digital filter audio filter pipelining register minimization field programmable gate array critical path

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