Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the r...
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Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the radial polynomials used to define them and the large inverse matrix calculation needed for the linear fit. This paper presents an efficient parallel method for calculating Zernike coefficients from phase gradients produced by a Shack-Hartman sensor and its real-time implementation using an FPGA by pre-calculation and storage of subsections of the large inverse matrix. The architecture exploits symmetries within the Zernike modes to achieve a significant reduction in memory requirements and a speed-up of 2.9 when compared to published results utilising a 2D-FFT method for a grid size of 8 x 8. Analysis of processor element internal word length requirements show that 24-bit precision in precalculated values of the Zernike mode partial derivatives ensures less than 0.5% error per Zernike coefficient and an overall error of < 1%. The design has been synthesized on a Xilinx Spartan-6 XC6SLX45 FPGA. The resource utilisation on this device is < 3% of slice registers, < 15% of slice LUTs, and approximately 48% of available DSP blocks independent of the Shack-Hartmann grid size. Block RAM usage is < 16% for Shack-Hartmann grid sizes up to 32 x 32.
In the state-of-the-art field-programmablegatearrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along wi...
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In the state-of-the-art field-programmablegatearrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.
Model predictive control (MPC) is nowadays considered a viable approach for high-speed control applications that require the controller to run autonomously on resourceconstrained computing devices. Many different type...
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Model predictive control (MPC) is nowadays considered a viable approach for high-speed control applications that require the controller to run autonomously on resourceconstrained computing devices. Many different types of such embedded devices exist allowing practitioners to trade-off performance, hardware cost, power consumption and other properties. This paper investigates the possibility to deploy a nonlinear MPC controller on a Xilinx Zynq- 7000 All programmable System on Chip, which features a dual-core ARM processor and a field-programmablegatearray (FGPA). We propose a specific choice of numerical algorithms that appears particularly suited for making best use of the hardware configuration at hand. Several variants of the proposed hybrid hardware implementation are compared to a naive deployment of the nonlinear MPC scheme on a single core of the CPU. Numerical experiments indicate that tailoring the NMPC scheme to exploit the advantages of both the CPU and the FPGA can considerably reduce both overall computation time and the feedback delay.
The paper presents the ring based Network on Chip (NoC) structure design and modeling in Hardware Description Language (HDL). The network configuration is chosen for 65536 nodes, which is synchronized with same clock ...
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The paper presents the ring based Network on Chip (NoC) structure design and modeling in Hardware Description Language (HDL). The network configuration is chosen for 65536 nodes, which is synchronized with same clock pulse. The functionality of each node is checked in Modelsim 10.1b software. The interprocess communication among nodes in verified using Virtex-5 FPGA. The priority of the nodes is assigned using FIFO logic, which is integrated with the NoC chip. The NoC architecture is based on token ring based network concept, called Rotator-on Chip (RoC). The design and modeling is done in Xilinx 14.2 ISE using VHDL programming language and synthesized on Digilent manufactured FPGA, with the target device, xc5vlx20t-2-ff323, Virtex-5. Hardware and timing parameters are extracted from the synthesized results and maximum frequency is found 535.733 MHz and memory utilization is 263208 kB.
Semaphore is a kind of mechanism used in a multithreaded environment to ensure that two or more key code segments are not concurrently invoked. In order to enhance the response capability of real-time operating system...
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Semaphore is a kind of mechanism used in a multithreaded environment to ensure that two or more key code segments are not concurrently invoked. In order to enhance the response capability of real-time operating systems, a hardware design scheme to implement semaphore management based on field programmable gate array is put forward in this paper. We take the mu C/OS-II real-time operating system as an example to design hardware logical circuits of semaphore management function module according to its parallel characteristics, and simulation tests under Xilinx ISE software environment are performed. The simulation results show that implementing semaphore management by hardware can obviously improve the execution time of creating/deleting a semaphore, applying for/releasing a semaphore and P/V operations;therefore, the whole reliability of the real-time operating system is greatly improved.
Solar power is the major renewable energy source opted by developing countries as stand-alone / Grid enabled system. Industries and educational institutions are opting for solar energy to combat power crisis. This pap...
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Solar power is the major renewable energy source opted by developing countries as stand-alone / Grid enabled system. Industries and educational institutions are opting for solar energy to combat power crisis. This paper proposes knowledge based, self configurable, smart controller to efficiently use solar energy according to load, under frequent grid failure environment. It is enabled with fault identification and isolation. Extension to higher power capacity is easily achieved with plug and play mechanism. Proposed control architecture is implemented using field programmable gate array (FPGA), that supports modular level implementation with well defined interfaces for each sub-system. It can be used with low power as well as high power photo-voltaic system. Efficiency of the proposed architecture is demonstrated for the photo-voltaic system installed in educational institution.
The programmable Logic Controller(PLC)-based Plant Protection System(PPS) in Nuclear Power Plants has the safety concerns,such as Common Cause Failure(CCF),complexity,and surveillance test *** analyzing the design con...
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The programmable Logic Controller(PLC)-based Plant Protection System(PPS) in Nuclear Power Plants has the safety concerns,such as Common Cause Failure(CCF),complexity,and surveillance test *** analyzing the design concept of the PPS in the perspective of CCF and complexity,this work describes the strategy based on diversity and defense in depth analyses to minimize the system complexity through structural and functional optimization for enhancing the *** diversity strategy involves separation of non-safety logics from PPS logics,adaptation of one-through channel test concept,and applying channel bypass *** are essential to implement simpler and easier hardware platform for both designers and operators to enhance the safety,reliability and economics compared to the PLC-based I&C safety system.
We evaluated the performance of a hardware architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a field programmable gate array(FPGA) co-...
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We evaluated the performance of a hardware architecture designed to perform a wide range of fast image processing tasks. The system architecture is based on hardware featuring a field programmable gate array(FPGA) co-processor and a host computer.A host application controlling a frame grabber and an industrial camera is used to capture and exchange video data with the hardware co-processor via a high speed USB3.0 channel,implemented with a standard macrocell, The FPGA accelerator is based on a XILINX kintex-7 chip and is designed as a system-on-a-programmable-chip with the help of an embedded software processor. The SOPC system integrates the CPU,external and on chip memory,the communication channel and typical image filters appropriate for the evaluation of the system *** transfer rates over the communication channel and processing times for the implemented hardware logic are presented for various frame sizes. A comparison with other solutions is given and a range of application is also discussed.
The paper focuses on a wireless myoelectric prosthesis of the upper-limb that uses a Multilayer Perceptron(MLP) neural network with back propagation algorithm in classifying electromyography(EMG) *** Neural network is...
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The paper focuses on a wireless myoelectric prosthesis of the upper-limb that uses a Multilayer Perceptron(MLP) neural network with back propagation algorithm in classifying electromyography(EMG) *** Neural network is composed of processing units that have the capability of sending signals to each other and perform a desired *** algorithm is widely used in pattern *** network is used to train EMG signals and use it in performing the necessary hand positions of the *** programming a field programmable gate array(FPGA) using Verilog and transmission of data with Zigbee,the EMG signals are acquired,classified,and simulated *** signals are classified and trained to produce the necessary hand *** corresponding hand movements of Open,Pick,Hold and Grip are simulated through the Zigbee controller.Z-test is used to analyze the data that were produced and acquired from using the neural network.
Multi-FPGA system for the design of the spiking neural network is a great challenge for hardware acceleration. Multilayer feedforward neural networks（FNNs） are vitally important for the study of the coding problems ...
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ISBN:
(纸本)9781467374439
Multi-FPGA system for the design of the spiking neural network is a great challenge for hardware acceleration. Multilayer feedforward neural networks（FNNs） are vitally important for the study of the coding problems in sensory organs. In this paper a multilayer FNN is implemented on a multi-FPGA-based system, which can guarantee both the high computational efficiency and the large network scale. The time-division multiplexing technology is employed in the proposed platform to be cost-efficient. In addition, since a parallel structure is used in the hardware design, the proposed hardware implementation can speedup approximately 4.8×104 times faster than the real-world biological behaviors in a high computational precision. Clock synchronization is considered in the design of the FNN to guarantee the accuracy of the signal transmission between layers. The proposed system can be applied to a broad kinds of fields such as the control of motors and the artificial intelligence, and the presented neurons can be replaced by more complicated neurons for the study of other dynamical characteristics of the neural networks.
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