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E-Health and Bioengineering Conference

作者： Iuliana CHIUCHISAN Department of Computer Science Automation and Electronics "Stefan cel Mare" University Suceava USV Suceava Romania

ISBN: (纸本)9781467375467

This paper presents a direct implementation and improvement of the real-time configurable system for image enhancement using Verilog Hardware Description Language and reconfigurable architecture (field programmable gate array). New series of filters are developed at the hardware level for image processing (edges detection, sharpen operation, enhance contrast operation and brightness-adjustment), in order to improve the quality of images and to assist in diagnosis the medical specialists. For verification and simulation of the Verilog-based system for image enhancement was used ISIM Simulator, a component of the ISE Design Suite program, from Xilinx. Using Hardware Description Languages for image processing is a quite new approach extending the field of digital design on reconfigurable circuits to digital image processing using VLSI technologies. Describing the image enhancement techniques using Verilog HDL enables rapid prototyping of these complex algorithms offering the direct possibility of FPGA implementation.

关键词： medical image enhancement Verilog hardware description language real-time configurable system field programmable gate array

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The safety review and formal verification on FPGA

The safety review and formal verification on FPGA

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作者： ZUO Jiaxu YU Wenzhuo LI Sen ZENG Hai ZHANG Chunming Department of Nuclear and Radiation Safety Research Nuclear and Radiation Safety Center MEP Special Risk Insurance Division PICC Property and Casualty Company Limited Engineering Center State Nuclear Power Automation System Engineering Corp

The FPGA technology is researched and developed in the reactor protection system. The FPGA system is developed by the software tools, and applications in the hardware. The safety review points of FPGA from NRC are introduced and some key points of FPGA's safety are discussed. The verification and validation, quality assurance and software tools seem more important for FPGA development. There are some disadvantages in the simulations of FPGA and the formal verification could be the usefully supplement for those disadvantages. Base on the SVA method in model checking of formal verification, the overpower ΔT trip chips were verified. And some bugs in ALU multiply modular were checked out and updated. Base on the SVA method, the formal verification makes the design and verification to take attentions on the function definition.

关键词： nuclear safety review simulation verification formal verification field programmable gate array

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Efficient Tree-Based Feature Descriptor and Matching Algorithm

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2014年第9期11卷 596-606页

作者： Fowers, Spencer Desai, Alok Lee, D. J. Ventura, Dan Wilde, Doran Microsoft Corp Redmond WA 98052 USA Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA Brigham Young Univ Dept Comp Sci Provo UT 84602 USA

This paper presents the development of a new feature descriptor derived from previous work on the basis sparse-coding inspired similarity descriptor that provides smaller descriptor size, simpler computations, faster matching speed, and higher accuracy. The TreeBASIS descriptor algorithm uses a binary vocabulary tree that is computed offline using basis sparse-coding inspired similarity dictionary images derived from sparse coding and a test set of feature region images. The resulting tree is stored in memory for online high-speed searching for feature matching. During the online matching stage, a feature region image is binary quantized and the resulting quantized vector is passed into the basis sparse-coding inspired similarity tree. A Hamming distance is computed between the feature region images and the effectively descriptive basis sparse-coding inspired similarity dictionary images at the current node to determine the branch taken. The path the feature region image takes is saved as the descriptor, and matching is performed by following the paths of two features and iteratively reducing the distance as the path is traversed. Experimental results show that the TreeBASIS descriptor is better than basis sparse-coding inspired similarity, scale invariant feature transform, and speeded-up robust features on frame-to-frame aerial feature point matching. It requires much less computational resources and runs faster.

关键词： Matching Algorithm Speeded Up Robust Features field programmable gate array Feature Detection Computing Application Programming Interface UAV Aeroplane Unmanned Ground Vehicle Random Access Memory

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PROSPECTS FOR RECONFIGURABLE SYSTEMS

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IEEE MICRO 2014年第1期34卷 72-78页

作者： Tredennick, Nick Shimamoto, Brion Univ Texas Austin Austin TX 78712 USA Univ Calif Los Angeles Los Angeles CA USA

IN 2003, THE AUTHORS PREDICTED THAT RECONFIGURABLE SYSTEMS WOULD EMERGE WITHIN 10 YEARS. THEY EXPECTED THE ARRIVAL OF A "HOLY GRAIL" MEMORY COMPONENT AND CHIP AND WAFER STACKING. THESE ADVANCES DID NOT OCCUR. RECONFIGURABLE SYSTEMS SHOULD APPEAR IN MARKETS WHERE EQUIPMENT HAS ACCESS TO CONTINUOUS POWER, BUT FINANCIAL INCENTIVES AND THE LACK OF A VERSATILE MEMORY COMPONENT INHIBIT THEIR EMERGENCE IN MOBILE SYSTEMS.

关键词： Reconfigurable Architectures field programmable gate arrays Random Access Memory Transistors Mobile Handsets Signal Processing Algorithms Value Transistor Reconfigurable Systems Reconfigurable Computing field programmable gate array FPGA Value PC

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FPGA-based embedded platform for fiber optic gyroscope signal denoising

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2014年第7期42卷 744-757页

作者： Peesapati, Rangababu Sabat, Samrat L. Karthik, K. P. Narasimhappa, M. Giribabu, N. Nayak, J. Univ Hyderabad Sch Phys Hyderabad 500046 Andhra Pradesh India Res Ctr Imarat Hyderabad 500069 Andhra Pradesh India

This paper presents System on Chip (SoC) implementation of a proposed denoising algorithm for fiber optic gyroscope (FOG) signal. The SoC is developed using an Auxillary Processing Unit of the proposed algorithm and implemented in the Xilinx Virtex-5-FXT-1136 field programmable gate array. SoC implementation of this application is first of its kind. The proposed algorithm namely adaptive moving average-based dual-mode Kalman filter (AMADMKF) is a hybrid of adaptive moving average and Kalman filter (KF) technique. The performance of the proposed AMADMKF algorithm is compared with the discrete wavelet transform and KF of different gains. Allan variance analysis, standard deviation and signal to noise ratio (SNR) are used to measure the efficiency of the algorithm. The experimental result shows that AMADMKF algorithm reduces the standard deviation or drift of the signal by an order of 100 and improves the SNR approximately by 80 dB. The Allan variance analysis result shows that this algorithmalso reduces different types of random errors of the signal significantly. The proposed algorithm is found to be the best suited algorithm for denoising the FOG signal in both the static and dynamic environments. Copyright (c) 2013 John Wiley & Sons, Ltd.

关键词： fiber optic gyroscope discrete wavelet transform Kalman filter Allan variance field programmable gate array auxiliary processing unit system on chip

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An Architecture for Coexistence with Multiple Users in Frequency Hopping Cognitive Radio Networks

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 2014年第3期32卷 563-571页

作者： McLean, Ryan K. Silvius, Mark D. Hopkinson, Kenneth M. Flatley, Bridget N. Hennessey, Ethan S. Medve, Curtis C. Thompson, Jared J. Tolson, Matthew R. Dalton, Clark V. Air Force Inst Technol Dept Elect & Comp Engn Wright Patterson AFB OH 43433 USA

The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency. One alternative is to incorporate reconfigurability within a cognitive radio platform, thereby enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively observe the RF spectrum, orient itself to the current RF environment, decide on a mode of operation, and act accordingly, thereby sharing the spectrum and operating in more a flexible manner. This research presents a novel architecture for the purpose of adapting radio operation to the current RF spectrum environment. Specifically, this research makes three contributions: (1) a framework for testing and evaluating clustering algorithms in the context of cognitive radio networks, (2) a new RF spectrum map merging technique for adaptive waveform selection, with initial integration testing on a field-programmable gate array (FPGA), and (3) a novel cognitive radio network emulation framework for testing and evaluating totally-ordered multicast as a means for inter-node communication.

关键词： Cognitive radio adaptive waveform clustering radio environment map multicast field programmable gate array

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FPGA-based high accuracy burst carrier frequency measurement method

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ELECTRONICS LETTERS 2014年第14期50卷 1026-U74页

作者： Zhang, Peng Wang, Houjun Li, Li Wang, Ping Univ Elect Sci & Technol China Sch Automat Engn Chengdu 611731 Peoples R China China Elect Technol Grp Corp Res Inst 10 Dept Aviat Chengdu 610036 Peoples R China

A burst carrier frequency measurement scheme combined with a timestamping counting method based on a field programmable gate array (FPGA) is proposed. With the multiplication and phase shift of count clock, multiple parallel counters are continuously counted, and the times of the rising edge of the unknown frequency f(x) are counted simultaneously. To obtain the frequency of f(x), linear regression by use of least-squares line fitting is used. Experimental results show that the proposed approach can effectively reduce the error introduced by the quantisation error of +/- 1, improve measurement accuracy by about 2 to 3 bit, reduce measurement uncertainty by more than 20% and diminish the processing time to 200 ns compared with the traditional methods under the same conditions.

关键词： FPGA-based high accuracy burst carrier frequency measurement method Other topics in statistics Measurement theory linear regression count clock multiplication shift multiple parallel counters Logic circuits measurement uncertainty Frequency measurement field programmable gate arrays Interpolation and function approximation (numerical analysis) measurement uncertainty reduction least squares approximations field programmable gate array regression analysis count clock phase shift timestamping counting method frequency measurement least-squares line fitting

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Efficient implementation of iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver using minimum-mean-square error interference cancellation

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IET COMMUNICATIONS 2014年第7期8卷 990-999页

作者： Han, Bing Yang, Zengli Zheng, Yahong Rosa Missouri Univ Sci & Technol Dept Elect & Comp Engn Rolla MO 65409 USA

An efficient hardware implementation scheme is proposed for iterative multi-input-multi-output orthogonal frequency-division multiplexing receiver which includes an MMSE-IC (minimum-mean-square error interference cancellation) detector, a channel estimator, a low-density parity-check (LDPC) decoder and other supporting modules. The proposed implementation uses the QR decomposition (QRD) of the complex-valued matrices with four coordinate rotation digital computer (CORDIC) cores and a back substitution to solve the MMSE-IC equations while the existing systolic array architectures require 15-38 CORDIC cores to achieve a similar throughput. The proposed 4-CORDIC QRD architecture can be configured as a 16-matrix or a 64-matrix pipelining by using a different number of multipliers combined with one-dimensional (1D) or 2D arrays of the back substitution, respectively. The channel estimator implements a commonly-used frequency domain least squares channel estimation with the canonic-signed-digits method, thanks to the character of the Zadroff-Chu sequence used as the pilot. In the LDPC decoder, the min-sum algorithm is implemented for the quasicyclic LDPC decoding. The two schemes for the MMSE-IC detector with different throughput and resource usages have been implemented in a field programmable gate array for a complete baseband turbo receiver. Their resource usages, throughputs and latencies are compared with the classic systolic array architectures, which demonstrate that the proposed receiver architecture achieves the best tradeoff between the throughput and the resource usage.

关键词： iterative methods MIMO communication OFDM modulation least mean squares methods interference suppression channel estimation parity check codes digital arithmetic systolic arrays frequency-domain analysis field programmable gate arrays cyclic codes decoding radiofrequency interference iterative multiple-input multiple-output orthogonal frequency-division multiplexing receiver minimum mean square error interference cancellation hardware implementation scheme MMSE-IC detector low-density parity-check decoder LDPC decoder QR decomposition complex-valued matrices coordinate rotation digital computer cores CORDIC cores MMSE-IC equations 4-CORDIC QRD architecture one-dimensional arrays 2D arrays 1D arrays frequency domain least square channel estimation canonic-signed-digit method Zadroff-Chu sequence character min-sum algorithm quasicyclic LDPC decoding resource usages field programmable gate array baseband turbo receiver classic systolic array architectures receiver architecture

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Development of mass spectrometry by high energy focused heavy ion beam: MeV SIMS with 8 MeV Cl⁷⁺ beam

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION B-BEAM INTERACTIONS WITH MATERIALS AND ATOMS 2014年 332卷 22-27页

作者： Jeromel, Luka Siketic, Zdravko Potocnik, Nina Ogrinc Vavpetic, Primoz Rupnik, Zdravko Bucar, Klemen Pelicon, Primoz Jozef Stefan Inst SI-1000 Ljubljana Slovenia Rudjer Boskovic Inst Zagreb 10000 Croatia LOTRIC Metrol Ltd SI-4227 Selca Slovenia

Particle induced X-ray emission (PIXE) at microprobe of jozef Stefan Institute is used to measure two-dimensional quantitative elemental maps of biological tissue. To improve chemical and biological understanding of the processes in vivo, supplementary information about chemical bonding and/or molecular distributions could be obtained by heavy-ion induced molecular desorption and a corresponding mass spectroscopy with Time-Of-Flight (TOF) mass spectrometer. As the method combines the use of heavy focused ions in MeV energy range and TOF Secondary Ion Mass Spectrometry, it is denoted as MeV SIMS. At jozef Stefan Institute, we constructed a linear TOF spectrometer and mount it to our multipurpose nuclear microprobe. A beam of 8 MeV Cl-35(7+) could be focused to a diameter of better than 3 mu m x 3 mu m and pulsed by electrostatic deflection at the high-energy side of accelerator. TOF mass spectrometer incorporates an 1 m long drift tube and a double stack microchannel plate (MCP) as a stop detector positioned at the end of the drift path. Secondary ions are focused at MCP using electrostatic cylindrical einzel lens. Time of flight spectra are currently acquired with a single-hit time-to-digital converter. Pulsed ion beam produces a shower of secondary ions that are ejected from positively biased target and accelerated towards MCP. We start our time measurement simultaneously with the start of the beam pulse. Signal of the first ion hitting MCP is used to stop the time measurement. Standard pulses proportional to the time of flight are produced with time to analog converter (TAC) and fed into analog-to-digital converter to obtain a time histogram. To enable efficient detection of desorbed fragments with higher molecular masses, which are of particular interest, we recently implemented a state-of art field programmable gate array (FPGA)-based multi-hit TOF acquisition. To test the system we used focused 8 MeV Cl-35(7+) ion beam with pulse length of 180 ns. Mass resoluti

关键词： Mass spectrometry Focused ion beam field programmable gate array Micro-PIXE MeV-SIMS Dual imaging mode

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20-Bit RISC and DSP System Design in an FPGA

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COMPUTING IN SCIENCE & ENGINEERING 2014年第2期16卷 16-20页

作者： Tomar, Amit Kumar Singh Jain, Rita Lakshmi Narain College of Technology India Lakshmi Narain College of Technology India

Today, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer core with several operations performed by a digital signal processor system. Here, the design of a RISC and DSP system is presented that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.

关键词： Reduced Instruction Set Computing field programmable gate arrays Registers Discrete Cosine Transforms Discrete Fourier Transforms Digital Signal Processing Logic gates Scientific Computing Arithmetic Logic Unit ALU CPU Control Unit CU field programmable gate array FPGA General Purpose Register GPR Instruction Register IR Program Counter PC Reduced Instruction Set Computer RISC Register Set RS Multiply And Accumulates MA Cs Very Large Instruction Word VLIW

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