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An efficient hybrid learning algorithm for neural network-based speech recognition systems on FPGA chip

NEURAL COMPUTING & APPLICATIONS 2014年第7-8期24卷 1879-1885页

作者： Pan, Shing-Tai Lan, Min-Lun Natl Univ Kaohsiung Dept Comp Sci & Informat Engn Kaohsiung 811 Taiwan Shu Te Univ Inst Comp Sci & Informat Engn Kaohsiung 824 Taiwan

This paper implemented an artificial neural network (ANN) on a field programmable gate array (FPGA) chip for Mandarin speech measurement and recognition of nonspecific speaker. A three-layer hybrid learning algorithm (HLA), which combines genetic algorithm (GA) and steepest descent method, was proposed to fulfill a faster global search of optimal weights in ANN. Some other popular evolutionary algorithms, such as differential evolution, particle swarm optimization and improve GA, were compared to the proposed HLA. It can be seen that the proposed HLA algorithm outperforms the other algorithms. Finally, the designed system was implemented on an FPGA chip with an SOC architecture to measure and recognize the speech signals.

关键词： field programmable gate array Genetic algorithm Hybrid learning algorithm Speech recognition

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Performance analysis of enhanced adaptive logic module for high performance FPGA architecture

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Research Journal of Applied Sciences, Engineering and Technology 2015年第3期9卷 215-223页

作者： Kishor Sonti, V.J.K. Varthamanan, Y. Sivaraman, D. Department of E.C.E. Sathyabama University Chennai Tamilnadu India M. Tech VLSI Design Sathyabama University Chennai Tamilnadu India

The Enhanced Adaptive Logic Module for High Performance field programmable gate array Architecture has been designed to increase the speed and reduces the device utilization of FPGA Architecture. The existing altera based adaptive logic module has eight input critical path look up tables. That means six inputs are given directly to the one Lookup table and two inputs are given to the other LUT by shorting any two from the first LUT of that six inputs. So that the delays has been increased. The proposed EALM has 8 fracturable direct input LUT, so eight input logic function can be implement by using this module with high speed than the altera based ALM. In this method only one LUT is used and it produces single output. Thus there is no need of carry logic, so that the area has been reduced and increases the speed. And FPGA architecture is formed by combining four adaptive logic modules using programmable interconnect array. Enhanced adaptive logic module is introduced in that architecture instead of adaptive logic module and the performance is analyzed. The adaptive logic modules and enhanced adaptive logic modules of field programmable gate array architecture has been designed and simulated by using Xilinx ISE 12.1. © 2015, Maxwell Scientific Organization.

关键词： Adaptive logic module Enhanced adaptive logic module field programmable gate array Lookup table programmable interconnect array

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Digital Receiver-based Electronic Intelligence System Configuration for the Detection and Identification of Intrapulse Modulated Radar Signals

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DEFENCE SCIENCE JOURNAL 2014年第2期64卷 152-158页

作者： Singh, A. K. Rao, K. Subba Def Elect Res Lab Hyderabad 500005 Andhra Pradesh India Osmania Univ Hyderabad 500075 Andhra Pradesh India

An optimum electronic intelligence system configuration incorporating the state of the art technologies and achieving the highest parameter accuracies while processing the complex intrapulse modulated radar signals is presented in this paper. The system is based on the quad digital receiver, a state of the art single board solution for the detection and analysis of modern radar signals. The system consists of base line interferometry configuration for high accuracy direction finding measurement with sector selection based on amplitude direction finding technique. Advanced signal processing algorithms with time frequency analysis are implemented in real time in field programmable gate array to extract all the basic as well as advanced parameters of frequency and phase modulations such as chirp, barker, and poly-phase (Frank, P1-P4) codes in addition to the pulse and continuous wave signals. The intercepted intrapulse modulated signal parameters have been extracted with very high accuracy and sensitivity.

关键词： Electronic intelligence quad digital receiver analog to digital converter field programmable gate array electronic warfare fast Fourier transform intrapulse

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GIVING TEXT ANALYTICS A BOOST

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IEEE MICRO 2014年第4期34卷 6-14页

作者： Polig, Raphael Atasu, Kubilay Chiticariu, Laura Hagleitner, Christoph Hofstee, H. Peter Reiss, Frederick R. Zhu, Huaiyu Sitaridi, Eva IBM Res Zurich Res Lab Zurich Switzerland IBM Res Intelligent Informat Syst Grp Zurich Switzerland IBM Res Accelerator Technol Grp Zurich Switzerland IBM Res Zurich Switzerland Columbia Univ Dept Comp Sci New York NY 10027 USA

TRADITIONAL SERVER ARCHITECTURES CANNOT ANALYZE BIG DATA EFFICIENTLY. BY USING A STREAMING HARDWARE ACCELERATOR IMPLEMENTED IN RECONFIGURABLE LOGIC, THE AUTHORS CAN IMPROVE THE THROUGHPUT OF SYSTEMT'S INFORMATION EXTRACTION QUERIES BY AN ORDER OF MAGNITUDE. SUCH A SYSTEM CAN BE DEPLOYED BY EXTENDING SYSTEMT'S EXISTING COMPILATION FLOW AND USING A MULTITHREADED COMMUNICATION INTERFACE THAT CAN UTILIZE THE ACCELERATOR'S BANDWIDTH.

关键词： Big Data Multi Threading Query Processing Reconfigurable Architectures Text Analysis User Interfaces Multithreaded Communication Interface Compilation Flow Throughput Rates Reconfigurable Logic Streaming Hardware Accelerator Bandwidth Big Data Information Extraction Query Based Interface Text Analytics System IBM System T Software Textual Data field programmable gate arrays Instruction Sets Big Data Text Processing Computer Architecture Text Mining Text Analytics Big Data field programmable gate array Heterogeneous System Hardware Accelerator Hardware

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Interlaced photoacoustic and ultrasound imaging system with real-time coregistration for ovarian tissue characterization

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JOURNAL OF BIOMEDICAL OPTICS 2014年第7期19卷 76020页

作者： Alqasemi, Umar Li, Hai Yuan, Guangqian Kumavor, Patrick Zanganeh, Saeid Zhu, Quing King Abdulaziz Univ Dept Elect & Comp Engn Jeddah 21589 Saudi Arabia Univ Connecticut Dept Biomed Engn Storrs CT 06269 USA Univ Connecticut Dept Elect Storrs CT 06269 USA Univ Connecticut Dept Comp Engn Storrs CT 06269 USA

Coregistered ultrasound (US) and photoacoustic imaging are emerging techniques for mapping the echogenic anatomical structure of tissue and its corresponding optical absorption. We report a 128-channel imaging system with real-time coregistration of the two modalities, which provides up to 15 coregistered frames per second limited by the laser pulse repetition rate. In addition, the system integrates a compact transvaginal imaging probe with a custom-designed fiber optic assembly for in vivo detection and characterization of human ovarian tissue. We present the coregistered US and photoacoustic imaging system structure, the optimal design of the PC interfacing software, and the reconfigurable field programmable gate array operation and optimization. Phantom experiments of system lateral resolution and axial sensitivity evaluation, examples of the real-time scanning of a tumor-bearing mouse, and ex vivo human ovaries studies are demonstrated. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： coregistered ultrasound and photoacoustic imaging ovarian cancer field programmable gate array peripheral component interconnect express interfacing reconfigurable computing

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Novel intelligent real-time position tracking system using FPGA and fuzzy logic

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ISA TRANSACTIONS 2014年第2期53卷 402-414页

作者： Soares dos Santos, Marco P. Ferreira, J. A. F. Univ Aveiro Dept Mech Engn Ctr Mech Technol & Automat TEMA P-3810193 Aveiro Portugal

The main aim of this paper is to test if FPGAs are able to achieve better position tracking performance than software-based soft real-time platforms. For comparison purposes, the same controller design was implemented in these architectures. A Multi-state Fuzzy Logic controller (FLC) was implemented both in a Xilinx (R) Virtex-II FPGA (XC2v1000) and in a soft real-time platform NI CompactRIO (R)-9002. The same sampling time was used. The comparative tests were conducted using a servo-pneumatic actuation system. Steady-state errors lower than 4 mu m were reached for an arbitrary vertical positioning of a 6.2 kg mass when the controller was embedded into the FPGA platform. Performance gains up to 16 times in the steady-state error, up to 27 times in the overshoot and up to 19.5 times in the settling time were achieved by using the FPGA-based controller over the software-based FLC controller. (C) 2013 ISA. Published by Elsevier Ltd. All rights reserved.

关键词： Automation field programmable gate array Fuzzy logic Real-time control systems Pneumatics Position tracking Control

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Heuristic Search-Based Framework for Onboard Trajectory Redesign

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2014年第1期37卷 164-175页

作者： Trumbauer, Eric Villac, Benjamin Univ Calif Irvine Dept Mech & Aerosp Engn Irvine CA 92697 USA

This paper presents a framework for automated impulsive transfer design with a view toward onboard application. A database of periodic orbits and other structurally important trajectories is combined with large-scale simulations to create a discrete representation of the system dynamics. A heuristic search is used to quickly find paths in this discretization, which generate a set of arcs and impulses approximating a continuous transfer between boundary conditions specified in the original system. Differential correction and partial optimization are used to create a final, feasible transfer. Each step will be described, with a focus on the construction of a weighted, directed graph representation of the transfer problem, as well as the search process and its relation to the final transfer.

关键词： Periapsis Search Algorithm Dijkstra's Algorithm Structural Element Libration Points Space Technology Roadmap Orbital Elements Boundary Value Problems Europa field programmable gate array

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Memory-efficient SURF architecture for ASIC implementation

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ELECTRONICS LETTERS 2014年第15期50卷 1059-1060页

作者： Lee, Sang-Seol Jang, Sung-Joon Kim, Jungho Hwang, Youngbae Choi, Byeongho KETI Multimedia IP Res Ctr Songnam South Korea

Among the image features for object recognition, speeded up robust features (SURF) have been widely implemented due to their hardware-friendly characteristics and high accuracy. However, because of adopting a fully internal memory-based architecture and a field programmable gate array having large memories for a high performance, most of them are infeasible to the application specific integrated chip (ASIC). A memory-efficient architecture for implementing SURF in ASIC by analysing the characteristics of memory accesses of SURF is presented. In addition, a strategy of dividing an entire image into multiple sub-images, processing them sequentially and overlapping each other to reduce the size of the internal memory while minimising the loss of information is proposed. The proposed architecture was implemented with 767 kb-sized internal memories and 1.2 M logic gates while processing 60 frames per second.

关键词： FPGA image features speeded up robust features memory access characteristics field programmable gate array application specific integrated circuits multiple sub-images information loss Semiconductor integrated circuits field programmable gate arrays storage capacity 767 Kbit Logic circuits Logic and switching circuits memory-efficient SURF architecture application specific integrated chip ASIC object recognition Computer vision and image processing techniques hardware-friendly characteristics memory architecture logic gates Image recognition

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Cost-effective sampling clock synchronisation scheme with its implementation in optical orthogonal frequency division multiplexing systems

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IET COMMUNICATIONS 2014年第5期8卷 639-645页

作者： Chen, Junchao Li, Yingchun Song, Yingxiong Zhang, Qianwu Shanghai Univ Key Lab Specialty Fiber Opt & Opt Access Networks Shanghai 200072 Peoples R China Bangor Univ Sch Elect Engn Bangor LL57 1UT Gwynedd Wales

A cost-effective scheme for sampling clock synchronisation based on the interpolation algorithm is proposed and implemented via field programmable gate array (FPGA). This scheme can provide a simpler and more economical achievement than the schemes that utilise expensive external clock recovery circuits. Low system complexity is another advantage of the proposed scheme due to the utilisation of the results of the frame synchronisation. Besides, a novel fractional sampling interval calculating algorithm which aims to calculate the fractional sampling time offset in a sampling interval is also proposed and this simpler operation algorithm based on least squares method is proved to fully satisfy the multi-subcarrier characteristic of orthogonal frequency division multiplexing (OFDM) symbol. The design and experimental results of a 2.5 Gb/s FPGA-based optical OFDM receiver by using the scheme that was proposed earlier are presented here. A major improvement in this scheme for sampling clock synchronisation is demonstrated to be suitable for practical application.

关键词： field programmable gate array optical modulation optical orthogonal frequency division multiplexing systems interpolation Modulation and coding methods OFDM modulation field programmable gate arrays cost-effective sampling clock synchronisation scheme least squares method Laser beam modulation, pulsing and switching least squares approximations mode locking and tuning fractional sampling interval calculating algorithm low system complexity interpolation algorithm expensive external clock recovery circuits Multiplexing and switching in optical communication Interpolation and function approximation (numerical analysis) frame synchronisation synchronisation FPGA-based optical OFDM receiver

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field programmable gate-array-based real-time optical Doppler tomography system for in vivo imaging of cardiac dynamics in the chick embryo

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OPTICAL ENGINEERING 2009年第2期48卷

作者： Thrane, Lars Larsen, Henning E. Norozi, Kambiz Pedersen, Finn Thomsen, Jakob B. Trojer, Maja Yelbuz, Talat Mesud Tech Univ Denmark Dept Photon Engn DTU Fotonik DK-4000 Roskilde Denmark Hannover Med Sch Dept Pediat Cardiol & Intens Care Med D-30625 Hannover Germany Lund Inst Technol Dept Phys SE-22100 Lund Sweden

We demonstrate a field programmable gate-array-based real-time optical Doppler tomography system. A complex-valued bandpass filter is used for the first time in optical coherence tomography signal processing to create the analytic signal. This method simplifies the filter design, and allows efficient and compact implementation by combining the conversion to an analytic signal with a pulse shaping function without the need for extra resources as compared to the Hilbert transform method. The conversion of the analytic signal to amplitude and phase is done by use of the coordinate rotation digital computer (CORDIC) algorithm, which is an efficient algorithm that maps well to the field programmable gate array. Flow phantom experiments, and the use of this system for in vivo imaging of cardiac dynamics in the chick embryo, are presented. We demonstrate the visualization of blood flow in the early embryonic heart as well as in the aorta, small peripheric vitelline vessels, and coronary arteries of fully formed chick hearts. (c) 2009 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3081062]

关键词： optical coherence tomography optical Doppler tomography digital signal processing field programmable gate array complex-valued bandpass filter

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