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Contribution to digital power factor correction controllers in high intensity discharge lamps electronic ballast applications

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IET POWER ELECTRONICS 2014年第7期7卷 1886-1894页

作者： Javier Diaz, Francisco Lopez, Victor M. Azcondo, Francisco J. Branas, Christian Casanueva, Rosario Univ Cantabria Syst & Automat Engn Dept E-39005 Santander Cantabria Spain

Utility voltage fluctuations not compensated by the low-frequency voltage loop of the power factor correction (PFC) stage cause a perceptible variation in the light emitted by lamps, unpleasant for the human eye and known as flicker effect. A novel extension of the digital control for PFC stages analyses the input voltage, detects the fluctuations in the range of human flicker sensitivity and modifies the PFC output voltage controller to avoid their propagation to the DC bus. The purpose of the controller is to make the PFC compatible with any second stage lamp driver, assuring the mitigation of the lamp light variation caused by utility disturbances in consistent with the human eye perception. The controller is implemented in a field programmable gate array. A constant lamp luminance is achieved with this digital controller with no dependence on the next ballast stage.

关键词： power factor correction digital control discharge lamps lamp accessories lighting control power control voltage control field programmable gate arrays digital power factor correction controller high intensity discharge lamp electronic ballast application utility voltage fluctuation compensation low-frequency voltage loop flicker effect digital control human flicker sensitivity PFC output voltage controller DC bus propagation second stage lamp driver lamp light variation mitigation human eye perception field programmable gate array constant lamp luminance

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programmable logic design of a compact Genetic Algorithm for phasor estimation in real-time

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ELECTRIC POWER SYSTEMS RESEARCH 2014年 107卷 109-118页

作者： Coury, D. V. Silva, R. P. M. Delbem, A. C. B. Casseb, M. V. G. Univ Sao Paulo Elect & Comp Eng Dept Sao Carlos Sch Engn BR-13566590 Sao Carlos SP Brazil Univ Sao Paulo Inst Math & Comp Sci BR-13566590 Sao Carlos SP Brazil

The main objective of this work is to present an efficient method for phasor estimation based on a compact Genetic Algorithm (cGA) implemented in field programmable gate array (FPGA). To validate the proposed method, an. Electrical Power System (EPS) simulated by the Alternative Transients Program (ATP) provides data to be used by the cGA. This data is as close as possible to the actual data provided by the EPS. Real life situations such as islanding, sudden load increase and permanent faults were considered. The implementation aims to take advantage of the inherent parallelism in Genetic Algorithms in a compact and optimized way, making them an attractive option for practical applications in real-time estimations concerning Phasor Measurement Units (PMUs). (C) 2013 Elsevier B.V. All rights reserved.

关键词： Phasor estimation Genetic algorithms field programmable gate array Alternative Transients Program

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Adaptive pulse signal shaping of tag response signal for RFID tag test system

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ELECTRONICS LETTERS 2014年第17期50卷 1182-1183页

作者： Hao, Jinguang Pei, Wenjiang Xia, Yili Wang, Kai Southeast Univ Sch Informat Sci & Engn Nanjing Jiangsu Peoples R China

An algorithm for adaptive pulse signal shaping is proposed for the tag response signal with large fluctuations of radio frequency identification (RFID) tag test systems, which has not been addressed in the literature for the scenario. To verify the proposed algorithm, an experimental platform implemented with a field programmable gate array (FPGA) is set up based on National Instruments. The experimental results show that the algorithm is sufficient for correcting the RFID tag response pulse signal even for the signal with severe signal distortion.

关键词： National Instruments FPGA RFID tag test system field programmable analogue arrays radiofrequency identification RFID systems Analogue processing circuits radio frequency identification distortion RFID tag response pulse signal tag response signal Signal processing and detection signal processing field programmable gate array adaptive pulse signal shaping signal distortion

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Hardware implementation of tag-reader mutual authentication protocol for RFID systems

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INTEGRATION-THE VLSI JOURNAL 2014年第1期47卷 123-129页

作者： Vijaykumar, V. R. Elango, S. Anna Univ Dept Elect & Commun Engn Coimbatore 641047 Tamil Nadu India Bannari Amman Inst Technol Dept Elect & Commun Engn Erode 638401 Tamil Nadu India

Radio-frequency identification (RFID) is a recent technology that utilizes radio frequencies to track the object by transmitting a signal with a unique serial identity. Generally, the drawbacks of RFID technology are high cost and authentication systems between a reader and a tag become weak. In this paper, we proposed a protocol for RFID tag-reader mutual authentication scheme which is hardware efficient and consumes less dynamic power. Truncated multipliers are implemented in RFID tag-reader mutual authentication protocol system due to reduction in hardware cost and dynamic power. Experimental evaluation reveals that the proposed protocol with truncated multipliers provides more security than the earlier schemes. The proposed protocol is described in VHDL and simulated using Altera Quartus II. The functional block is implemented as hardware using an Altera DE2 Cyclone II (EP2C35F672C6) field-programmable gate array (FPGA). (C) 2013 Elsevier B.V. All rights reserved.

关键词： Authentication protocol field programmable gate array RFID Linear feedback shift register Truncated multiplier

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RECONFIGURABLE COMPUTING Introduction

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IEEE MICRO 2014年第1期34卷 4-6页

作者： Najjar, Walid A. Ienne, Paolo Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

This introduction to the special section on Reconfigurable Computing briefly discusses the history and current state of the field and introduces the articles in the special section.

关键词： Special Issues And Sections Reconfigurable Architectures History Computer Architecture field programmable gate array Reconfigurable Computing FPGA

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Simplified embedded control scheme for two-stage multistring off-grid inverter

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IET POWER ELECTRONICS 2014年第12期7卷 2954-2963页

作者： Reddy, B. Dastagiri Selvan, Manickavasagam Parvathy Moorthi, Sridharan Natl Inst Technol EEE Dept Hybrid Elect Syst Lab Tiruchirappalli Tamil Nadu India

This study proposes an embedded control for an off-grid single-phase multistring inverter with front-end DC-DC conversion stage followed by a synchronised H-bridge. In this inverter, the duty cycle of DC-DC converter is varied in the form of fully rectified sinusoidal fashion to produce a similar output voltage across the DC-link capacitor. This unidirectional voltage is converted into an AC voltage by the synchronised H-bridge. An application of this inverter topology with the proposed control scheme in micro-grid is investigated in the present study. The proposed control scheme not only possesses better steady-state performance with both linear and non-linear loads but also provides fast dynamic response during a step change in load. A digital controller based on field programmable gate array is utilised for the simultaneous generation of high-frequency switching pulses for DC-DC converter and synchronised fundamental frequency switching pulses for H-bridge. The entire system is simulated in MATLAB/Simulink (R) environment and its functioning is verified with linear and non-linear loads. The hardware prototype of inverter is also built in the laboratory and its performance is validated. Further, the better performance of the proposed system for supplying household appliances is ascertained in the laboratory.

关键词： unidirectional voltage digital control field programmable gate array embedded control front-end DC–DC conversion stage Control of electric power systems Logic and switching circuits step change synchronised H-bridge Logic circuits AC voltage nonlinear loads load regulation embedded systems high-frequency switching pulses microgrid Power system control invertors duty cycle DC-link capacitor DC-DC power convertors MATLAB -Simulink environment off-grid single-phase multistring inverter field programmable gate arrays synchronised fundamental frequency switching pulses distributed power generation inverter topology dynamic response digital controller Distributed power generation

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Multi-beam RF aperture using multiplierless FFT approximation

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ELECTRONICS LETTERS 2014年第24期50卷 1788-U149页

作者： Suarez, D. Cintra, R. J. Bayer, F. M. Sengupta, A. Kulasekera, S. Madanayake, A. Univ Fed Pernambuco Dept Estat Signal Proc Grp Recife PE Brazil Univ Fed Santa Maria Dept Estat BR-97119900 Santa Maria RS Brazil Univ Fed Santa Maria LACESM BR-97119900 Santa Maria RS Brazil Univ Akron ECE Akron OH 44325 USA

Multiple independent radio-frequency (RF) beams find applications in communications, radio astronomy, radar and microwave imaging. An N-point fast Fourier transform (FFT) applied spatially across an array of receiver antennas provides N-independent RF beams at N/2 log(2) N multiplier complexity. Here, a low-complexity multiplierless approximation for the 8-point FFT is presented for RF beamforming, using only 26 additions. The algorithm provides eight beams that closely resemble the antenna array patterns of the traditional FFT-based beam-former albeit without using multipliers. The proposed FFT-like algorithm was verified on-chip using a Xilinx Virtex-6 Lx240T field programmable gate array (FPGA) device. The FPGA implementation indicated bandwidth of 369 MHz for each of the independent receive-mode RF beams.

关键词： multiplierless FFT approximation CMOS technology radar imaging RF multibeam receivers Radio links and equipment fast Fourier transform FFT based beamformer Antenna arrays RF beamforming antenna arrays FPGA device radio networks multibeam RF aperture Logic circuits multiplierless approximation field programmable gate arrays complementary metal oxide semiconductor multiplier complexity antenna array patterns multiple independent radio frequency radio astronomy RF beams approximation theory Interpolation and function approximation (numerical analysis) field programmable gate array CMOS simulation CMOS integrated circuits microwave imaging receiver antenna array Integral transforms in numerical analysis fast Fourier transforms

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Low read-only memory distributed arithmetic implementation of quaternion multiplier using split matrix approach

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ELECTRONICS LETTERS 2014年第24期50卷 1809-U173页

作者： Petrovsky, N. Stankevich, A. Petrovsky, A. BSUIR Minsk BELARUS

In most algorithms that use quaternion numbers, the key operation is a quaternion multiplication, of which the efficiency and accuracy obviously determine the same properties of the whole computational scheme of a filter or transform. A digit (L-bit)-serial quaternion multiplier based on the distributed arithmetic (DA) using the splitting of the multiplication matrix is presented. The circuit provides the facility to compute several products of quaternion components concurrently as well as to reduce the memory capacity by half in comparison with the known DA-based multiplier, and it is well suited for field programmable gate array (FPGA)-based fixed-point implementations of the algorithms. Apart from a theoretical development, the experimental design results which are obtained using a Xilinx Virtex 6 FPGA are reported.

关键词： Semiconductor storage split matrix Logic circuits Logic and switching circuits distributed arithmetic DA-based multiplier Xilinx Virtex 6 FPGA multiplication matrix Memory circuits Algebra quaternion multiplier matrix algebra quaternion multiplication ROM field programmable gate array field programmable gate arrays read-only storage

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A placer for composable FPGA with 2D mesh network

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2014年第4期6卷 289-302页

作者： Keung, Ka-Ming Ponpandi, Swamy D. Tyagi, Akhilesh Iowa State Univ Dept Elect & Comp Engn Ames IA 50010 USA

FPGAs are predominantly used for acceleration of computationally intensive algorithmic kernels. The ubiquitous co-processor abstraction, in which an application offloads such kernels to the FPGA, does not scale with current and future architectural advancements in FPGA technology. The rapid march of fabrication technology into the sub-micron era has resulted in packing of multiple blocks of programmable resources such as hard CPU cores, DSP modules, and fast multipliers on contemporary FPGA. Optimisation benefits from these advancements and the unique advantage of programmability have made FPGA an attractive alternative for complex system on chip (SoC) designs over other solutions. Adoption of the co-processor model in current generation of programmable architectures relegates the hard problem of hardware abstraction to the application and hence, the programmer. We propose a FPGA abstraction with native 2D-mesh network in order to improve the run time reconfigurability of multiple accelerators. In this paper, we describe a composable FPGA virtualisation framework to wean away the dependence of FPGA applications on the co-processor model. A novel run time placement algorithm, which minimises the communication energy between the accelerator modules, is evaluated on an embedded video application to demonstrate the placement efficiency in our framework.

关键词： reconfiguration field programmable gate array FPGA CLB placement embedded systems placer composable co-processor virtualisation accelerator on chip network mesh

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Multi-blocks scheme for high definition video display based on digital micro-mirror device

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ELECTRONICS LETTERS 2014年第22期50卷 1593-1594页

作者： Liu, Yiqing Sun, Li E China Normal Univ Shanghai Key Lab Multidimens Informat Proc Shanghai 200241 Peoples R China

The digital micro-mirror device (DMD) and its related techniques have been widely used in various projection equipments. The application of a high-resolution video display scheme based on the DMD is considered. The scheme has been implemented in hardware with a field programmable gate array (FPGA)-based platform, which organises and selects the visual data, and then feeds them into the micro-mirror chip for the projection display based on pulse width modulation (PWM). The proposed scheme divides the video frame into a set of blocks, and the arrays of digital mirrors in different blocks work in a sequential way, so that the needed bandwidth for transferring the image data can be reduced significantly without loss of visual quality.

关键词： image data transfer FPGA PWM digital micromirror device high-resolution video display scheme field programmable gate array data visualization Display technology high definition video field programmable gate arrays Logic circuits data visualisation DMD Micro-optical devices and technology pulse width modulation High definition television optical projectors micromirrors multiblock scheme Optical, image and video signal processing high definition video display projection equipment display instrumentation image resolution

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