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检索条件"主题词=Field Programmable Gate array"

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Predictive Control for Longitudinal Beam Dynamics in Heavy Ion Synchrotrons

Predictive Control for Longitudinal Beam Dynamics in Heavy I...

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IEEE Conference on Control Applications (CCA)

作者： Faulwasser, Timm Lens, Dieter Kellett, Christopher M. Ecole Polytech Fed Lausanne Lab Automat CH-1004 Lausanne Switzerland Tech Univ Darmstadt Inst Automatisierungstech D-64283 Darmstadt Germany Univ Newcastle Sch Elect Engn & Comp Sci Callaghan NSW 2308 Australia

ISBN: (纸本)9781479974092

We present a design of a predictive control scheme for longitudinal beam dynamics in heavy ion synchrotrons. Specifically, we consider a linear-quadratic model predictive control (MPC) approach, whereby the quadratic program is solved via a fast gradient method. Furthermore, we investigate whether the fast gradient method allows for real-time feasible implementation of the proposed approach on a field programmable gate array (FPGA). Our results indicate that sampling rates in the order of 1 MHz are achievable.

关键词： model predictive control heavy ion synchrotrons longitudinal beam control fast gradient method field programmable gate array

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An 1μm all-fiber based pulsed laser system incorporating an agile waveform tailoring driver 5

An 1μm all-fiber based pulsed laser system incorporating an...

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5 International Conference on Photonics (ICP)

作者： Ong, C. E. Ho, Y. H. Yeap, K. H. Lee, S. C. Teh, P. C. Teh, P. S. UTAR Fac Engn & Green Technol Dept Elect Engn Kajang Selangor Malaysia TFL Solut Ipoh Perak Malaysia

ISBN: (纸本)9781479948833

This paper describes a 1.06 mu m all-fiber based pulsed laser source incorporating an agile field programmable gate array (FPGA) based driver board, which has the capabilities to generate pulses with arbitrary shapes and controllable bursts. Optical pulse durations tunable from picoseconds to nanoseconds, as well as pulse frequency adjustments from 1kHz to 1MHz can be achieved. An average optical power of 1W can be obtained from the amplified system with the output optical pulses optimized by reshaping the input pulses using this agile waveform tailoring method.

关键词： field programmable gate array Fiber Laser Laser Micromachining

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Low Complex, programmable FPGA based 8-Channel Ultrasound Transmitter for Medical Imaging Researches 16

Low Complex, Programmable FPGA based 8-Channel Ultrasound Tr...

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16th IEEE International Conference on e-Health Networking, Applications and Services (Healthcom)

作者： Dusa, Chandrashekar Rajalakshmi, P. Puli, Suresh Desai, U. B. Merchant, S. N. Indian Inst Technol Hyderabad Dept Elect Engn Hyderabad Andhra Pradesh India Indian Inst Technol Dept Elect Engn Bombay Maharashtra India

ISBN: (纸本)9781479966448

In commercial ultrasound systems, the transmit module typically generates the time delayed excitation pulses to steer and focus the acoustic beam. However, the ultrasound transmitter module in these systems has limited access to medical ultrasound researchers. In this paper, we have presented the development of a programmable architecture for 8-channel ultrasound transmitter for medical ultrasound research activities. The proposed architecture consists of 8 transmit channels and field programmable gate array (FPGA) based configurable delay profile to steer acoustic beam, transmit frequency and pulse pattern length depending on the medical application. Our system operates in pulse-echo mode, with ultrasound transmit frequency up to 20 MHz, excitation voltage up to 100 Vpp, and individual channel control with single high speed Serial Peripheral Interface (SPI). Pre-calculated delay profiles per scanline are generated in Matlab, based on physical parameters of 8 element linear transducer array which are used to steer and focus the ultrasound beam. An experiment is carried with our transmit module to transmit ultrasound into gelatin phantom, acquired echoes and processed for B-mode imaging. The results show that this transmit platform can be used for ultrasound imaging researches and also for medical diagnosis.

关键词： Ultrasonic imaging ultrasonic transducer array field programmable gate array transmit beamformer high voltage pulser

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Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA

Impact of defect tolerance techniques on the criticality of ...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Blanchardon, Adrien Chotin-Avot, Roselyne Mehrez, Habib Amouri, Emna Univ Paris 06 Sorbonne Univ UMR 7606 LIP6 F-75005 Paris France CNRS UMR 7606 LIP6 F-75005 Paris France

ISBN: (纸本)9781479959440

As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add redundancy to propose defect-tolerant architectures. But, hardware redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAM-based Mesh of Clusters FPGA and different strategies to locally insert hardware redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic hardware redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).

关键词： SRAM chips fault tolerant computing field programmable gate arrays FPGA area overhead SRAM-based mesh criticality cluster FPGA critical path delay increase defect tolerance techniques defected manufactured circuits field programmable gate array hardware redundancy mesh-of-clusters architecture static random access memory Delays Distributed feedback devices field programmable gate arrays Hardware Multiplexing Redundancy Switches field programmable gate arrays Static random access storage redundancy Distributed feedback lasers Fault tolerant computing Computer hardware MULTIPLEXOR Criticality Switches Mesh Mesh Medical Subject Headings

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Glucose Level Regulation for Diabetes Mellitus Type 1 Patients using FPGA Neural Inverse Optimal Control 4

Glucose Level Regulation for Diabetes Mellitus Type 1 Patien...

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IEEE Symposium on Computational Intelligence in Control and Automation (CICA)

作者： Romero-Aragon, Jorge C. Sanchez, Edgar N. Alanis, Alma Y. CINVESTAV Unidad Guadalajara Zapopan 45019 Jalisco Mexico Univ Guadalajara CUCEI Zapopan 45080 Jalisco Mexico

ISBN: (纸本)9781479945306

In this paper, the field programmable gate array (FPGA) implementation of a discrete-time inverse neural optimal control for trajectory tracking is proposed to regulate glucose level for type 1 diabetes mellitus (T1DM) patients. For this controller, a control Lyapunov function (CLF) is proposed to obtain an inverse optimal control law in order to calculate the insulin delivery rate, which prevents hyperglycemia and hypoglycemia levels in T1DM patients. Besides this control law minimizes a cost functional. The neural model is obtained from an on-line neural identifier, which uses a recurrent high-order neural network (RHONN), trained with an extended Kalman filter (EKF). A virtual patient is implemented on a PC host computer, which is interconnected with the FPGA controller. This controller constitutes a step forward to develop an autonomous artificial pancreas.

关键词： Kalman filters Lyapunov methods discrete time systems diseases field programmable gate arrays medical computing medical control systems neurocontrollers nonlinear filters optimal control recurrent neural nets sugar CLF EKF FPGA controller FPGA neural inverse optimal control PC host computer RHONN T1DM patients autonomous artificial pancreas control Lyapunov function cost functional minimization diabetes mellitus type 1 patients discrete-time inverse neural optimal control extended Kalman filter field programmable gate array glucose level regulation hyperglycemia level hypoglycemia level insulin delivery rate inverse optimal control law neural model online neural identifier recurrent high-order neural network trajectory tracking type 1 diabetes mellitus patients virtual patient Covariance matrices field programmable gate arrays Mathematical model Optimal control Sugar field programmable gate arrays Optimal control Kalman filters Type 1 Diabetes Mellitus sugar trajectory tracking recurrent neural nets medical control systems chlorofibre Neurocontrollers medical computing discrete time systems Nonlinear filters Extended Kalman filters Lyapunov methods

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Integration of AES on Heterogeneous Many-Core system

Integration of AES on Heterogeneous Many-Core system

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22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

作者： Anwar, Hassan Daneshtalab, Masoud Ebrahimi, Masoumeh Ramirez, Marco Plosila, Juha Tenhunen, Hannu Univ Turku Dept Informat Technol Turku Finland

ISBN: (纸本)9781479927289

Increasing in the transistor density in a single chip makes it possible for many-core systems to utilize design space for implementing complex embedded systems. In this paper, we propose an architecture for heterogeneous many-core system to integrate block cipher algorithm which is based on Advanced Encryption Standard (AES). In order to implement AES as a crypto-core along with heterogeneous many-core system two different approaches are proposed. In the first approach, the platform is composed of an AES module, a crypto-core, a network interface, and an internal memory which are managed through a controller. In the second approach, the platform is composed of a Direct Memory Access (DMA), network interface, an internal memory, and a microprocessor in which the AES module is integrated as a crypto-core. Both approaches have been analyzed and compared in terms of area overhead and performance.

关键词： Many-Core field programmable gate array AES Network Interface Crypto-Core

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XML Data Interface and PMU Testing Applications for Synchrophasor Estimation with a Reconfigurable Controller 49

XML Data Interface and PMU Testing Applications for Synchrop...

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49th International Universities Power Engineering Conference (UPEC)

作者： Katsimichas, Anastasis Brogan, Paul Laverty, David Queens Univ Belfast EPIC Belfast BT7 1NN Antrim North Ireland

ISBN: (纸本)9781479965571

Phasor Measurement Unit (PMU) technology has rapidly improved over the last two decades. This development allowed a number of conventional protocols, both open and proprietary, to be written. Optimised communication and implementation techniques are sought by academia. This motivation has resulted in university projects, such as The OpenPMU project. The aim is to create a completely open source system that will be cost efficient, reliable, modular and platform independent. The discussed work is focused on the detailed description of a data interface XML based communication tool. The outlined schema is used to exchange data between the acquisition system and the phase estimation algorithm of a PMU. Its many advantages establish it as a flexible schema for transmitting sampled data irrespective of hardware or software implementation. The OpenPMU system is based on hardware implementations that use freely available DAQ devices and aim to develop a low cost alternative to commercial PMU's. The hardware described in this paper is based on a National Instruments field programmable gate array (FPGA) reconfigurable controller (cRIO) that due to its parallel nature can perform different processing operations at the same time. This results in higher speed and accuracy and should provide the benchmark for testing various existing and future OpenPMU implementations.

关键词： OpenPMU phasor measurement unit field programmable gate array National Instruments phasor estimation

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Implementation of high performance Advanced Encryption Standard-128 for WiMAX Application on FPGA 2

Implementation of high performance Advanced Encryption Stand...

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2nd IEEE International Symposium on Telecommunication Technologies (ISTT)

作者： Ahmad, Rafidah Ismail, Widad Univ Sains Malaysia Collaborat MicroElect Design Excellence Ctr CEDEC Engn Campus Nibong Tebal 14300 Penang Malaysia Univ Sains Malaysia Sch Elect & Elect Engn Auto ID Lab Nibong Tebal 14300 Penang Malaysia

ISBN: (纸本)9781479959822

Worldwide interoperability for microwave access (WiMAX) which is also known as IEEE 802.16 standard for broadband wireless access continues to gain popularity as a technology with a significant market potential. This development makes wireless security a very serious concern. Advanced encryption standard (AES) has been widely used for protection in WiMAX application. This study focuses on the implementation of high performance AES-128 algorithm with 128 -bit cipher key on field programmable gate array (FPGA) in terms of architectural and throughput differences as well as power consumption rates. Three different A ES -128 designs, including the proposed AES-128 design, are introduced and evaluated. Xilinx Virtex5 FPGA is utilized for implementation and verification purposes. Results show that with Virtex5 FPGA, the proposed AES-128 design reduces the slices by 2% and increases the throughput by 95% compared with the reference designs. The proposed AES-128 design also reduces total power consumption by 6% with Virtex5 FPGA.

关键词： worldwide interoperability for microwave access advanced encryption standard field programmable gate array perPrmance power

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Wiring Control by RTL Design for Reconfigurable Wave-Pipelined Circuits

Wiring Control by RTL Design for Reconfigurable Wave-Pipelin...

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Annual Summit and Conference of Asia-Pacific-Signal-and-Information-Processing-Association (APSIPA)

作者： Sato, Tomoaki Chivapreecha, Sorawat Moungnoul, Phichet Hirosaki Univ Comp & Networking Ctr Hirosaki Aomori Japan King Mongkuts Inst Technol Ladkrabang Dept Telecommun Engn Bangkok Thailand

ISBN: (纸本)9786163618238

High-speed and low-power circuits of considering the development cycle for digital signal processing are very important in a mobile computing. The achievement of them on an FPGA (field programmable gate array) dominant in the point of shortening the development cycle. Nevertheless a reconfigurable device such as an FPGA for a power-aware design has not been developed. The authors have developed logic blocks for reconfigurable wave-pipelined circuits for the achievement of high-speed and low-power reconfigurable circuits. Wave-pipeline is one of a circuit design technique for high-speed processing and low-power consumption. They are very useful for the reduction in the resource on the FPGA. However, a wiring control to connect them have not been achieved. In this paper, the wiring control by RTL Design is developed. Its operation speeds are evaluated using 0.18 um CMOS technology.

关键词： CMOS integrated circuits digital signal processing chips electronic engineering computing field programmable gate arrays logic design low-power electronics mobile computing pipeline processing wiring CMOS technology FPGA RTL circuit design technique digital signal processing field programmable gate array high-speed processing low-power circuits reconfigurable device reconfigurable wave pipelined circuits size 0.18 mum wiring control Abstracts Digital signal processing field programmable gate arrays Mobile computing Registers Switches Wiring

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System Simulation and Optimization using Reconfigurable Hardware 14

System Simulation and Optimization using Reconfigurable Hard...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Lukasiewycz, Martin Shreejith, Shanker Fahmy, Suhaib A. TUM CREATE Singapore Singapore Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781479948338

This paper presents a methodology for simulating and automatically optimizing distributed cyber-physical systems using reconfigurable hardware. By mapping an entire system of distributed devices including the buses onto a single field programmable gate array (FPGA), it becomes possible to make changes to the architecture, including the topology, using reconfiguration. This approach enables accurate rapid prototyping of distributed architectures, while also closing the gap between early simulation results and the final design, leading to a more robust optimization. Furthermore, the system can be simulated and optimized within a Hardware-in-the-Loop (HIL) setup due to its cycle-and bit-accurate execution in real-time. We introduce the general concept and building blocks that enable a faster and more accurate simulation and optimization: (1) The details of our approach for mapping devices, network interfaces, and buses onto an FPGA are presented. (2) An optimization model is proposed that encodes the topology, task distribution, and communication in a very efficient representation. Finally, the implementation and integration of the methodology is presented and discussed.

关键词： distributed processing field programmable gate arrays FPGA communication distributed architecture distributed cyber-physical systems field programmable gate array optimization model reconfigurable hardware system optimization system simulation task distribution topology Computer architecture Encoding field programmable gate arrays Hardware Integrated circuit modeling Optimization Routing field programmable gate arrays reconfigurable hardware systems simulation integrated circuit modelling system optimization Distributed processing Computer Architecture Computer hardware topology Network routing Communication Research

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