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检索条件"主题词=Field Programmable Gate array"

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FPGA Implementation of an Efficient and Highly Secure Cryptoprocessor over Barreto-Naehrig Curves

FPGA Implementation of an Efficient and Highly Secure Crypto...

引用

International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)

作者： Shyam, V Sujatha, D. KS Rangasamy Coll Technol Tiruchengode Namakkal India

ISBN: (纸本)9781479949816

Pairings such as Tate, Ate and Optimal-ate are used to perform operations over special form of elliptic curves known as Barreto-Naehrig (BN) curves. Computation of the pairings involve the floating point operations which is difficult to perform and for this purpose special hardware blocks are used. Existing techniques uses Montgomery multiplication algorithm which uses one hardware block corresponding to each operations. This results in increase in the area. Also these hardware blocks take more time to perform these computations. So this paper aims at 1) reducing the computation time of the cryptographic operations and 2) minimizing the hardware blocks required for performing the computations thereby reducing the area. A new dedicated Cryptoprocessor is proposed which consists of a single hardware unit to perform all the operations. The implementation results on a Virtex-4 FPGA device shows that it consumes 23k Slices and computes the tate pairing in 16.475ns.

关键词： Cryptoprocessor Pairing Computations field programmable gate array Elliptic Curve Cryptography

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FPGA Based Design of a Fine-Grained Fault Tolerant Interleaved Memory

FPGA Based Design of a Fine-Grained Fault Tolerant Interleav...

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International Conference on Advanced Communication Control and Computing Technologies*

作者： Das, Somak Dey, Sowvik Univ Burdwan Univ Inst Technol Dept Comp Sci & Engn Burdwan W Bengal India

ISBN: (纸本)9781479939145

Memory bandwidth has been the bottleneck of modern computing systems with the advent of increasing processor speed. High speed processors engage themselves dealing data access with comparatively low speed memories resulting poor processor utilizing. Development of a high speed memory system is therefore a challenging domain of research. The concept of interleaved memory systems with high throughput plays a pivotal role in bridging the speed gap between processor and memory. Exploiting fault tolerance within an interleaved memory system makes it functionally more reliable with a trade-off in speed. Word level bypassing of the fault location is a fine grained approach of fault tolerance that can reduce wastage of significant amount of address space. FPGA based design and implementation of such a fault tolerant interleaved memory is proposed in this paper.

关键词： Memory bandwidth processor utilization interleaved memory fault tolerance fine grain field programmable gate array hardware description language test bench waveform

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Realization of 1024 points fast Fourier transform based on FPGA IPCore

Realization of 1024 points fast Fourier transform based on F...

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4th International Conference on Frontiers of Manufacturing and Design Science (ICFMD 2013)

作者： Leng Jianwei Xu Qiongqiong Tianjin Univ Technol Tianjin Key Lab Control Theory & Applicat Complic Tianjin Peoples R China Tianjin Univ Technol Sch Elect Engn Tianjin Peoples R China

ISBN: (纸本)9783037859926

Requirement on signal processing of radar level system is higher and higher at present. Standards such as generalization, systematic and modular cannot be satisfied through traditional methods which were using software program, application specific integrated circuit (ASIC) to achieve fast flourier transform (FFT). Therefore taking advantage of field programmable gate array (FPGA) to complete FFT had been the choosing trend of most researchers. Based on arithmetic FFT raised by Cooley-Tukey, a new design scheme of base-4 FFT was put forward in this paper. The design flow of FFT was fairly simple for the rich resource and flexible intellectual property core (IP Core). Simulation and experiment results indicated that this method was easy and flexible, accuracy and reliable. And it can decrease the development period. The calculation speed was also improved greatly.

关键词： signal procession fast flourier transform field programmable gate array intellectual property core

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Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA

Embedding FPGA Overlays into Configurable Systems-on-Chip: R...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Wiersema, Tobias Bockhorn, Arne Platzner, Marco Univ Paderborn Paderborn Germany

ISBN: (纸本)9781479959440

Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.

关键词： field programmable gate arrays operating systems (computers) system-on-chip virtualisation FPGA overlay ReconOS operating system ZUMA-based virtual FPGA fabric configurable systems-on-chip field programmable gate array nonvirtualized circuitry physical FPGA virtualized circuitry Computer architecture field programmable gate arrays Hardware Message systems Routing Software Video recording

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Design of Configurable, Network Based Interconnection Modules for Communication Centric System-On-Chip Applications

Design of Configurable, Network Based Interconnection Module...

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IEEE Symposium on Computer Applications and Industrial Electronics (ISCAIE)

作者： Mishra, Prabhakar Nidhi, A. Kishore, J. K. Kotturshettar, Chetan PES Inst Technol Ctr Intelligent Syst Bangalore Karnataka India Indian Space Res Org Bangalore 562140 Karnataka India Texas Instruments Inc Bangalore Karnataka India

ISBN: (纸本)9781467351591

In recent years, System-on-Chip design architectures have increasingly become communication centric. To support such designs, a configurable and scalable interconnect backbone is required. Intellectual Property cores for on chip communication, provided by major field programmable gate array vendors are limited to shared bus or point to point interconnect protocols. To provide network oriented interconnect fabric, we propose a configurable and scalable, network based interconnect module. The interconnections can be configured to four popular on-chip network topologies: mesh, torus, ring and fat-tree. A parameterized and customizable wormhole router is designed, with variable number of ports and link width to support the four networks. A hardware simulator has been designed for in-situ testing of the interconnect module. Two state of art implementation platforms viz Virtex-6 field programmable gate array and a full custom implementation using 32nm CMOS process has been used to characterize the module. We report area and power dissipation of the module configured to the four topologies, in the two platforms.

关键词： Application Specific Integrated Circuit field programmable gate array Networks-On-Chip System-On-Chip

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Parameterized AES-based Crypto Processor for FPGAs 17

Parameterized AES-based Crypto Processor for FPGAs

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17th Euromicro Conference on Digital System Design (DSD)

作者： Anwar, Hassan Daneshtalab, Masoud Ebrahimi, Masoumeh Dytckov, Sergei Plosila, Juha Tenhunen, Hannu Beltrame, Giovanni Univ Turku Dept Informat Technol SF-20500 Turku Finland Ecole Polytech Montreal Montreal PQ Canada

ISBN: (纸本)9781479957934

In this paper, we propose a parameterized crypto co-processor based on Advanced Encryption Standard (AES). This parameterized AES module is combined with a 32-bit general purpose 5-stage pipelined MIPS processor. The AES module used in this paper is fully pipelined. The processor fetches an instruction from the instruction memory and sends it to the decode stage. If the instruction is the crypto instruction it is pushed into the AES module during the decode stage. However if the instruction belongs to the MIPS processor, the remaining cycles will be completed on the MIPS processor. The parameterized AES module has different latencies on different rounds of AES according to the application requirements. The effects of different number of rounds on latency, memory, and area are studied and reported.

关键词： Cryptographic field programmable gate array Parameterized AES pipeline Processor

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Fast data transmission in dynamic data acquisition system for plasma diagnostics

Fast data transmission in dynamic data acquisition system fo...

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Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments

作者： Byszuka, Adrian Pozniak, Krzysztof Zabolotny, Wojciech M. Kasprowicz, Grzegorz Wojenski, Andrzej Cieszewski, Radoslaw Juszczyk, Bartlomiej Kolasinski, Piotr Zienkiewicz, Pawel Chernyshova, Maryna Czarski, Tomasz Warsaw Univ Technol Fac Elect & Informat Technol PL-00655 Warsaw Poland Inst Plasma Phys & Laser Microfus PL-01497 Warsaw Poland

ISBN: (纸本)9781628413694

This paper describes architecture of a new data acquisition system (DAQ) targeted mainly at plasma diagnostic experiments. Modular architecture, in combination with selected hardware components, allows for straightforward reconfiguration of the whole system, both offline and online. Main emphasis will be put into the implementation of data transmission subsystem in said system. One of the biggest advantages of described system is modular architecture with well defined boundaries between main components: analog frontend (AFE), digital backplane and acquisition/control software. Usage of a FPGA chips allows for a high flexibility in design of analog frontends, including ADC. FPGA interface. Data transmission between backplane boards and user software was accomplished with the use of industry-standard PCI Express (PCIe) technology. PCIe implementation includes both FPGA firmware and Linux device driver. High flexibility of PCIe connections was accomplished due to use of configurable PCIe switch. Whenever it's possible, described DAQ system tries to make use of standard off-the-shelf (OTF) components, including typical x86 CPU & motherboard (acting as PCIe controller) and cabling.

关键词： field programmable gate array FPGA PCI Express DAQ systems

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Test and Measurement Planning For Active Antennas

Test and Measurement Planning For Active Antennas

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IEEE Conference on Antenna Measurements and Applications (CAMA)

作者： Masters, Gregory F. Nearfield Syst Inc Business Dev Torrance CA 90502 USA

ISBN: (纸本)9781479936786

Active Antennas are becoming more and more popular. Antennas that efficiently control amplitude and phase distribution as well as polarization have become standard in large phased arrays. Industry trends of low-cost sensors and increased computing power from field programmable gate arrays (FPGA) have made it possible to manipulate antenna apertures in real-time. Add the ability to provide pulsed RF, digital beam forming and/or polarization diversity and the antenna aperture becomes an antenna system controlling a highly customizable electromagnetic surface. In order to test antenna systems with this type of capability, special consideration for testing must be made during system design time. Understanding some of the latest active antenna techniques available today is invaluable to saving time, money and protecting proprietary information.

关键词： active antenna arrays antenna phased arrays antenna radiation patterns antenna testing aperture antennas array signal processing field programmable gate arrays telecommunication industry FPGA active antenna measurement planning active antenna testing amplitude control antenna aperture manipulation customizable electromagnetic surface digital beam forming field programmable gate array low-cost sensor industry trend money saving phase distribution control phased array antenna polarization control polarization diversity proprietary information protection pulsed RF time saving Antenna measurements Probes Pulse measurements Radio frequency Receiving antennas Testing field programmable gate arrays antenna phased arrays aperture antennas digital beam forming active antennas polarization diversity pulse measurement Telecommunications industry Receiving antennas Antenna measurements antenna radiation patterns radiofrequency array signal processing AMPLITUDE CONTROL Probes

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Low-cost, high-performance and efficiency computational photometer design

Low-cost, high-performance and efficiency computational phot...

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Conference on Multisensor, Multisource Information Fusion - Architectures, Algorithms, and Applications

作者： Siewert, Sam B. Shihadeh, Jeries Myers, Randall Khandhar, Jay Ivanov, Vitaly Univ Alaska Anchorage 3211 Providence Dr Anchorage AK 99508 USA BUnivers Colorado Boulder Boulder CO 80309 USA Mentor Graph Corp Boulder CO 80501 USA

ISBN: (纸本)9781628410587

Researchers at the University of Alaska Anchorage and University of Colorado Boulder have built a low cost high performance and efficiency drop-in-place Computational Photometer (CP) to test in field applications ranging from port security and safety monitoring to environmental compliance monitoring and surveying. The CP integrates off-the-shelf visible spectrum cameras with near to long wavelength infrared detectors and high resolution digital snapshots in a single device. The proof of concept combines three or more detectors into a single multichannel imaging system that can time correlate read-out, capture, and image process all of the channels concurrently with high performance and energy efficiency. The dual-channel continuous read-out is combined with a third high definition digital snapshot capability and has been designed using an FPGA (field programmable gate array) to capture, decimate, down-convert, re-encode, and transform images from two standard definition CCD (Charge Coupled Device) cameras at 30Hz. The continuous stereo vision can be time correlated to megapixel high definition snapshots. This proof of concept has been fabricated as a four-layer PCB (Printed Circuit Board) suitable for use in education and research for low cost high efficiency field monitoring applications that need multispectral and three dimensional imaging capabilities. Initial testing is in progress and includes field testing in ports, potential test flights in un-manned aerial systems, and future planned missions to image harsh environments in the arctic including volcanic plumes, ice formation, and arctic marine life.

关键词： photometer infrared field programmable gate array multichannel stereo vision depth mapper

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Study on High Frequency Inverter With 100kHz Current Feedback Control by Using FPGA 17

Study on High Frequency Inverter With 100kHz Current Feedbac...

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17th IEEE International Conference on Electrical Machines and Systems (ICEMS)

作者： Amano, Shunsuke Akatsu, Kan Shibaura Inst Technol Tokyo Japan

ISBN: (纸本)9781479951628

This paper reports the effectiveness of high frequency 100kHz Pulse Width Modulation (PWM) inverter with the current feedback control adopted for Permanent Magnet Synchronous Motor (PMSM) and Switched Reluctance Motor (SRM). Advantages of the high frequency current feedback control are verified in this paper. First, the motor loss reduction in a PMSM is verified, and second, a method to drive the low inductance motor is considered by driving low inductance SRM. The effectiveness of these methods is verified by the experiments.

关键词： PWM invertors electric current control feedback field programmable gate arrays machine control permanent magnet motors reluctance motors synchronous motors FPGA PMSM current feedback control field programmable gate array frequency 100 kHz high frequency PWM inverter low inductance SRM motor loss reduction permanent magnet synchronous motor pulse width modulation inverter switched reluctance motor field programmable gate arrays Frequency control Inverters Permanent magnet motors Reluctance motors Stators

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