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28th European Frequency and Time Forum (EFTF)

作者： Wouters, Michael J. Marais, Louis Natl Measurement Inst Lindfield NSW Australia

ISBN: (纸本)9781479952526

The National Measurement Institute, Australia has been developing methods for time and frequency transfer over optical fibre with an eye towards applications in radio-astronomy. We report here on a digital time-transfer system that uses pseudo-random noise-ranging and is implemented on a field programmable gate array. The system has demonstrated a time deviation of a few ps on a 100 km link.

关键词： field programmable gate arrays frequency measurement optical fibres optical noise radioastronomy time measurement Australia National Measurement Institute digital time-transfer system distance 100 km field programmable gate array frequency transfer optical fibre pseudorandom noise ranging radio-astronomy Clocks Correlation Delays field programmable gate arrays Modems Optical interferometry Temperature measurement

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Low-cost, high-performance and efficiency computational photometer design

Low-cost, high-performance and efficiency computational phot...

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Conference on Multisensor, Multisource Information Fusion - Architectures, Algorithms, and Applications

作者： Siewert, Sam B. Shihadeh, Jeries Myers, Randall Khandhar, Jay Ivanov, Vitaly Univ Alaska Anchorage 3211 Providence Dr Anchorage AK 99508 USA BUnivers Colorado Boulder Boulder CO 80309 USA Mentor Graph Corp Boulder CO 80501 USA

ISBN: (纸本)9781628410587

Researchers at the University of Alaska Anchorage and University of Colorado Boulder have built a low cost high performance and efficiency drop-in-place Computational Photometer (CP) to test in field applications ranging from port security and safety monitoring to environmental compliance monitoring and surveying. The CP integrates off-the-shelf visible spectrum cameras with near to long wavelength infrared detectors and high resolution digital snapshots in a single device. The proof of concept combines three or more detectors into a single multichannel imaging system that can time correlate read-out, capture, and image process all of the channels concurrently with high performance and energy efficiency. The dual-channel continuous read-out is combined with a third high definition digital snapshot capability and has been designed using an FPGA (field programmable gate array) to capture, decimate, down-convert, re-encode, and transform images from two standard definition CCD (Charge Coupled Device) cameras at 30Hz. The continuous stereo vision can be time correlated to megapixel high definition snapshots. This proof of concept has been fabricated as a four-layer PCB (Printed Circuit Board) suitable for use in education and research for low cost high efficiency field monitoring applications that need multispectral and three dimensional imaging capabilities. Initial testing is in progress and includes field testing in ports, potential test flights in un-manned aerial systems, and future planned missions to image harsh environments in the arctic including volcanic plumes, ice formation, and arctic marine life.

关键词： photometer infrared field programmable gate array multichannel stereo vision depth mapper

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Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA

Impact of defect tolerance techniques on the criticality of ...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Blanchardon, Adrien Chotin-Avot, Roselyne Mehrez, Habib Amouri, Emna Univ Paris 06 Sorbonne Univ UMR 7606 LIP6 F-75005 Paris France CNRS UMR 7606 LIP6 F-75005 Paris France

ISBN: (纸本)9781479959440

As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add redundancy to propose defect-tolerant architectures. But, hardware redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAM-based Mesh of Clusters FPGA and different strategies to locally insert hardware redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic hardware redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).

关键词： SRAM chips fault tolerant computing field programmable gate arrays FPGA area overhead SRAM-based mesh criticality cluster FPGA critical path delay increase defect tolerance techniques defected manufactured circuits field programmable gate array hardware redundancy mesh-of-clusters architecture static random access memory Delays Distributed feedback devices field programmable gate arrays Hardware Multiplexing Redundancy Switches field programmable gate arrays Static random access storage redundancy Distributed feedback lasers Fault tolerant computing Computer hardware MULTIPLEXOR Criticality Switches Mesh Mesh Medical Subject Headings

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A novel architecture for dynamic Integral Image generation for Haar-based face detection on FPGA

A novel architecture for dynamic Integral Image generation f...

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IEEE Region 10 Conference (TENCON)

作者： Kumar, Chanchal Agarwal, Sankalp Indian Inst Technol Dept Elect & Commun Engn Roorkee Uttarakhand India

ISBN: (纸本)9781479940752

Integral Image generation is an important step in the Haar-based face detection algorithm and plays a vital role in the optimization of the algorithm for real-time implementation by evaluating each of the thousands of Haar-features in constant time. The integral image of a frame needs to be generated as a pre-processing stage before running the Haar-classifier on the detection windows within the frame. The delay required in the pre-processing stage is directly proportional to the resolution of the frame and becomes substantial with increasing resolution, limiting the real-time operation of the entire algorithm. This paper presents a novel architecture for generating the integral images of the current detection window dynamically, such that the pre-processing delay is reduced substantially. It is shown that an improvement of 13.71 times is obtained for VGA frames by this approach. The usage of hardware resources is also reduced by around 50% compared to previous implementations.

关键词： Haar transforms face recognition feature extraction field programmable gate arrays image classification image resolution integral equations FPGA Haar-based face detection algorithm Haar-classifier Haar-features VGA frames detection windows dynamic integral image generation architecture field programmable gate array frame resolution hardware resources usage image preprocessing delay image preprocessing stage optimization Clocks Delays Face Feature extraction Generators Image generation Image resolution field programmable gate arrays Image generation image resolution Facial Recognition Feature extraction Haar transforms Timing devices Image classification Integral equations dynamos Face Face delay

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2014 International Symposium on Computer Architecture Influential Paper Award

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IEEE MICRO 2014年第6期34卷 94-95页

作者： Keckler, Stephen W. Nvidia University of California San Diego

This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper "PipeRench: A Coprocessor for Streaming Mu... 详细信息

关键词： Awards Ravi Rajwar ISCA Influential Paper Award Pipe Rench field programmable gate array FPGA Reconfigurable Logic Virtualization Maurice Wilkes Award

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Integration of AES on Heterogeneous Many-Core system

Integration of AES on Heterogeneous Many-Core system

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22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

作者： Anwar, Hassan Daneshtalab, Masoud Ebrahimi, Masoumeh Ramirez, Marco Plosila, Juha Tenhunen, Hannu Univ Turku Dept Informat Technol Turku Finland

ISBN: (纸本)9781479927289

Increasing in the transistor density in a single chip makes it possible for many-core systems to utilize design space for implementing complex embedded systems. In this paper, we propose an architecture for heterogeneous many-core system to integrate block cipher algorithm which is based on Advanced Encryption Standard (AES). In order to implement AES as a crypto-core along with heterogeneous many-core system two different approaches are proposed. In the first approach, the platform is composed of an AES module, a crypto-core, a network interface, and an internal memory which are managed through a controller. In the second approach, the platform is composed of a Direct Memory Access (DMA), network interface, an internal memory, and a microprocessor in which the AES module is integrated as a crypto-core. Both approaches have been analyzed and compared in terms of area overhead and performance.

关键词： Many-Core field programmable gate array AES Network Interface Crypto-Core

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An 1μm all-fiber based pulsed laser system incorporating an agile waveform tailoring driver 5

An 1μm all-fiber based pulsed laser system incorporating an...

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5 International Conference on Photonics (ICP)

作者： Ong, C. E. Ho, Y. H. Yeap, K. H. Lee, S. C. Teh, P. C. Teh, P. S. UTAR Fac Engn & Green Technol Dept Elect Engn Kajang Selangor Malaysia TFL Solut Ipoh Perak Malaysia

ISBN: (纸本)9781479948833

This paper describes a 1.06 mu m all-fiber based pulsed laser source incorporating an agile field programmable gate array (FPGA) based driver board, which has the capabilities to generate pulses with arbitrary shapes and controllable bursts. Optical pulse durations tunable from picoseconds to nanoseconds, as well as pulse frequency adjustments from 1kHz to 1MHz can be achieved. An average optical power of 1W can be obtained from the amplified system with the output optical pulses optimized by reshaping the input pulses using this agile waveform tailoring method.

关键词： field programmable gate array Fiber Laser Laser Micromachining

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An FPGA Based Architecture for Concurrent System Design Applied to Human-robot Interaction Applications 21

An FPGA Based Architecture for Concurrent System Design Appl...

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21st ISPE Inc International Conference on Concurrent Engineering

作者： Zhang, Lin Slaets, Peter Bruyninckx, Herman Katholieke Univ Leuven Dept Mech Engn B-3000 Leuven Belgium Int Univ Coll Grp T B-3000 Leuven Belgium

ISBN: (纸本)9781614994404;9781614994398

This paper presents a hardware and software architecture for vision-based human-robot interaction designed for field programmable gate array (FPGA) based embedded system. The configurable logic and memory blocks connected through programmable interconnects on the FPGA permit programmers to create complex systems running multiple processing cores in parallel, which motivated the authors to implement vision algorithms and robot controllers on a single system-on-chip (SoC) board, aiming at low cost, low power consumption and high performance in human-robot interaction for industrial and educational robots. The architecture is a product derived from a component based programming model together with a systematic methodology for concurrent system design proposed by the authors.

关键词： field programmable gate array embedded system concurrent system design vision based robot control software and hardware architecture

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Wiring Control by RTL Design for Reconfigurable Wave-Pipelined Circuits

Wiring Control by RTL Design for Reconfigurable Wave-Pipelin...

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Annual Summit and Conference of Asia-Pacific-Signal-and-Information-Processing-Association (APSIPA)

作者： Sato, Tomoaki Chivapreecha, Sorawat Moungnoul, Phichet Hirosaki Univ Comp & Networking Ctr Hirosaki Aomori Japan King Mongkuts Inst Technol Ladkrabang Dept Telecommun Engn Bangkok Thailand

ISBN: (纸本)9786163618238

High-speed and low-power circuits of considering the development cycle for digital signal processing are very important in a mobile computing. The achievement of them on an FPGA (field programmable gate array) dominant in the point of shortening the development cycle. Nevertheless a reconfigurable device such as an FPGA for a power-aware design has not been developed. The authors have developed logic blocks for reconfigurable wave-pipelined circuits for the achievement of high-speed and low-power reconfigurable circuits. Wave-pipeline is one of a circuit design technique for high-speed processing and low-power consumption. They are very useful for the reduction in the resource on the FPGA. However, a wiring control to connect them have not been achieved. In this paper, the wiring control by RTL Design is developed. Its operation speeds are evaluated using 0.18 um CMOS technology.

关键词： CMOS integrated circuits digital signal processing chips electronic engineering computing field programmable gate arrays logic design low-power electronics mobile computing pipeline processing wiring CMOS technology FPGA RTL circuit design technique digital signal processing field programmable gate array high-speed processing low-power circuits reconfigurable device reconfigurable wave pipelined circuits size 0.18 mum wiring control Abstracts Digital signal processing field programmable gate arrays Mobile computing Registers Switches Wiring

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System Simulation and Optimization using Reconfigurable Hardware 14

System Simulation and Optimization using Reconfigurable Hard...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Lukasiewycz, Martin Shreejith, Shanker Fahmy, Suhaib A. TUM CREATE Singapore Singapore Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781479948338

This paper presents a methodology for simulating and automatically optimizing distributed cyber-physical systems using reconfigurable hardware. By mapping an entire system of distributed devices including the buses onto a single field programmable gate array (FPGA), it becomes possible to make changes to the architecture, including the topology, using reconfiguration. This approach enables accurate rapid prototyping of distributed architectures, while also closing the gap between early simulation results and the final design, leading to a more robust optimization. Furthermore, the system can be simulated and optimized within a Hardware-in-the-Loop (HIL) setup due to its cycle-and bit-accurate execution in real-time. We introduce the general concept and building blocks that enable a faster and more accurate simulation and optimization: (1) The details of our approach for mapping devices, network interfaces, and buses onto an FPGA are presented. (2) An optimization model is proposed that encodes the topology, task distribution, and communication in a very efficient representation. Finally, the implementation and integration of the methodology is presented and discussed.

关键词： distributed processing field programmable gate arrays FPGA communication distributed architecture distributed cyber-physical systems field programmable gate array optimization model reconfigurable hardware system optimization system simulation task distribution topology Computer architecture Encoding field programmable gate arrays Hardware Integrated circuit modeling Optimization Routing field programmable gate arrays reconfigurable hardware systems simulation integrated circuit modelling system optimization Distributed processing Computer Architecture Computer hardware topology Network routing Communication Research

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