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检索条件"主题词=Field Programmable Gate array"

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A Technical Review of Software Defined Radios: Vision, Reality, and Current Status 33

A Technical Review of Software Defined Radios: Vision, Reali...

引用

33rd Annual IEEE Military Communications Conference on Affordable Mission Success - Meeting the Challenge (MILCOM)

作者： Goeller, Lawrence Tate, David Inst Def Analyses Cost Anal & Res Div Alexandria VA USA

ISBN: (纸本)9781479967704

Since the 1980s, the US military has been seeking a way to improve the ease and flexibility of communications within and between the Services. Forces deployed at that time used dozens of different radios, most of which could only communicate with other radios of the same type. Software Defined Radio (SDR) offered the promise of not only interoperating with all existing radios, but also allowing those legacy radios to communicate with each other. Just as important, SDR would enable future communications systems to be implemented on already-deployed hardware. This vision of interoperability and forward compatibility has not been realized, despite billions of dollars of investment in the Joint Tactical Radio System (JTRS). The authors reviewed JTRS program archives and studied the hardware and software architectures to determine whether there are fundamental technical reasons behind this failure. Our findings, which invoke the familiar tradeoff between performance and power consumption, are summarized in this paper. We identify three different architectural approaches used by the JTRS community over the years, and discuss why none has been able to realize the program's goals.

关键词： Software defined radio joint tactical radio system waveform portability field programmable gate array software communications architecture

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Development of Volumetric Display Based on Multi-Bit Color LED

Development of Volumetric Display Based on Multi-Bit Color L...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Hirayama, Ryuji Nakayama, Hirotaka Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Shiraki, Atsushi Chiba Univ Grad Sch Engn Chiba Japan Kisarazu Natl Coll Technol Dept Informat & Comp Engn Chiba Japan

ISBN: (纸本)9781479952304

We developed a 24-bit color volumetric display based on light emitting diode (LED). This volumetric display consists of 8 x 8 x 8 LEDs array and can represent 24-bit color three-dimensional images. The light intensity of the LEDs is gradated by the pulse width modulation method. We designed a control circuit of the volumetric display with the field programmable gate array. We succeeded in displaying 24-bit color three-dimensional moving image.

关键词： volumetric display light emitting diode pulse width modulation field programmable gate array

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Embedded Empirical Mode Decomposition Intellectual Property Core

Embedded Empirical Mode Decomposition Intellectual Property ...

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22nd IEEE Signal Processing and Communications Applications Conference (SIU)

作者： Horasanli, Nida Celebi, Anil Kocaeli Univ Elekt & Haberlesme Muhendisligi Bolumu Kocaeli Turkey

ISBN: (纸本)9781479948741

In this paper an embedded empirical mode decomposition (EMD) core with industry standard microprocessor interface is proposed. The core developed can easily be integrated with an embedded microprocessor system without any hardware level modifications. It can be easily utilized by using simple handles as part of the main software running on the microprocessor. The communication interface of the developed core performs two functions. First, it performs the control operations between the core and the microprocessor. It performs receiving the data as stream from the outside world and drives the computation results to the output as a second function. The core's functionality can be easily utilized by using simple software handles.

关键词： Advanced eXtensible Interface AXI Empirical Mode Decomposition EMD field programmable gate array FPGA VLSI

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A novel architecture for dynamic Integral Image generation for Haar-based face detection on FPGA

A novel architecture for dynamic Integral Image generation f...

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IEEE Region 10 Conference (TENCON)

作者： Kumar, Chanchal Agarwal, Sankalp Indian Inst Technol Dept Elect & Commun Engn Roorkee Uttarakhand India

ISBN: (纸本)9781479940752

Integral Image generation is an important step in the Haar-based face detection algorithm and plays a vital role in the optimization of the algorithm for real-time implementation by evaluating each of the thousands of Haar-features in constant time. The integral image of a frame needs to be generated as a pre-processing stage before running the Haar-classifier on the detection windows within the frame. The delay required in the pre-processing stage is directly proportional to the resolution of the frame and becomes substantial with increasing resolution, limiting the real-time operation of the entire algorithm. This paper presents a novel architecture for generating the integral images of the current detection window dynamically, such that the pre-processing delay is reduced substantially. It is shown that an improvement of 13.71 times is obtained for VGA frames by this approach. The usage of hardware resources is also reduced by around 50% compared to previous implementations.

关键词： Haar transforms face recognition feature extraction field programmable gate arrays image classification image resolution integral equations FPGA Haar-based face detection algorithm Haar-classifier Haar-features VGA frames detection windows dynamic integral image generation architecture field programmable gate array frame resolution hardware resources usage image preprocessing delay image preprocessing stage optimization Clocks Delays Face Feature extraction Generators Image generation Image resolution field programmable gate arrays Image generation image resolution Facial Recognition Feature extraction Haar transforms Timing devices Image classification Integral equations dynamos Face Face delay

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Comparison of AC Mains Synchronization Methods when Using Precalculated Duty Cycles in Power Factor Correction

Comparison of AC Mains Synchronization Methods when Using Pr...

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IEEE 15th Workshop on Control and Modeling for Power Electronics (COMPEL)

作者： Sanchez, Alberto de Castro, Angel Lopez-Colino, Fernando Garrido, Javier Univ Autonoma Madrid HCTLab E-28049 Madrid Spain

ISBN: (纸本)9781479921478

Classic PFC (Power Factor Correction) converters usually have three sensors: input voltage, input current and output voltage. Instead of using these three measures to calculate the duty cycle, precalculated duty cycles can be stored in a memory. With this memory, the system only has to synchronize with the ac mains and apply the duty cycles, at least for nominal conditions. This paper shows several methods to accomplish this synchronization, using an ADC or a voltage comparator. Results show that PFC can be achieved using simple synchronization methods and precalculated duty cycles.

关键词： Power Factor Correction (PFC) field programmable gate array Sensor-less control

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Design of an FPGA-Based Full-State Feedback Controller Using High Level Synthesis Tools

Design of an FPGA-Based Full-State Feedback Controller Using...

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IEEE 15th Workshop on Control and Modeling for Power Electronics (COMPEL)

作者： Velazquez, R. Lucia, O. Navarro, D. Barragan, L. A. Artigas, J. I. Sagues, C. Univ Zaragoza Dept Elect Engn & Commun Zaragoza Spain Univ Zaragoza Dept Informat & Syst Engn Zaragoza Spain

ISBN: (纸本)9781479921478

Digital control has significantly advanced in the last decade enabling the implementation of higher performance controllers using digital devices such as microcontrollers, DSPs or FPGAs. The design and implementation of controllers using FPGAs is often a challenging and time-consuming task. In order to improve this process, high level synthesis tools allow the use of high-level programming languages, easing the design and simulation process and enabling a straight-forward design space exploration. This paper details the overall design process using high level synthesis tools and presents as a representative example a full-state feedback controller for a buck converter using single-precision floating point representation. The main implementation and experimental results are summarized, highlighting the main benefits and drawbacks of this approach.

关键词： Digital control field programmable gate array Hardware description language High level synthesis

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Design of a Fault Tolerant Low-Order Interleaved Memory Based on the Concept of Bubble-Stack An Image Storage Perspective

Design of a Fault Tolerant Low-Order Interleaved Memory Base...

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18th International Symposium on VLSI Design and Test

作者： Das, Somak Dey, Sowvik Univ Burdwan Univ Inst Technol Dept Comp Sci & Engn Burdwan 713104 W Bengal India

ISBN: (纸本)9781479940066

Memory access rates have been the shortfall of modern computing systems with increasing processor speed. High speed processors do not perform as expected due to relative low data access rates of the concerned memory. Development of a memory system with higher accessing speed is therefore the need of hour. The concept of low-order interleaved memory systems with high throughput neutralises the speed gap between processor and memory. Interleaved memory systems can also be designed in a high-order fashion to make it fault tolerant. But, a fault tolerant high-order interleaved memory lacks the speed advantage. Therefore, designing a high speed low-order interleaved memory with properties of fault tolerance remained as a challenging area of research since decades. This paper proposes a design of low-order interleaved memory system which displays a high degree of fault tolerance without compromise in speed and storage space.

关键词： Memory bandwidth processor utilization interleaved memory bubble-stack fault tolerance fine grain field programmable gate array

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An Efficient Implementation of 2-D Discrete Wavelet Transform for high speed DSP applications 5

An Efficient Implementation of 2-D Discrete Wavelet Transfor...

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5th IEEE International Conference on Computational Intelligence and Computing Research (IEEE ICCIC)

作者： Mandloi, Aditya Boyat, Ajay Medi Caps Inst Technol & Management Elect & Commun Indore Madhya Pradesh India

ISBN: (纸本)9781479939756

This paper presents an efficient VLSI architecture of a high speed, low power two dimensional Discrete Wavelet Transform (2-D DWT). The proposed work minimizes the resource requirement and complexity of system. Design modules were realized using basic wavelet in HDL language and MATLAB for optimizing the speed and memory requirements. The system is modeled and implemented using Xilinx VirtexE FPGA device. The simulation results obtained through Mentor graphics simulation software. The system computing rate is up to 290 M samples/s and design uses only 34.376ns combinational path delay for 8x8 image size. In this way, the developed design provides very high-speed processing.

关键词： Discrete Wavelet Transform (DWT) image compression field programmable gate array VHDL

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Performance Analysis of DA Based Adaptive FIR Filter Using FPGA 11

Performance Analysis of DA Based Adaptive FIR Filter Using F...

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11th Annual IEEE India Conference (INDICON)

作者： Singh, Harpreet Singh, Gurinder Singh, Tarandip Sri Guru Granth Sahib World Univ Dept Elect Engn Fatehgarh Sahib 140406 India

ISBN: (纸本)9781479953646

In this paper, the performance is analyzed based on operating speed, area and memory requirement for the least mean square (LMS) adaptive finite impulse response (FIR) filter using distributed arithmetic (DA). DA technique performs the convolution operation by replacing multipliers with look up tables that result in low resource utilization and high throughput. The throughput and resource utilization factors are related with the number of taps in the DA base unit and these DA base units are required to reduce the memory size and to provide fast updating of memory contents. In this paper, we also analyzed the effect of the number of taps in DA base unit on the memory usage and operating speed of the adaptive FIR filter design.

关键词： Distributed Arithmetic Least Mean Square field programmable gate array Digital Signal Processing.

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Nonlinear Voltage Control for Motion State Detection in Solenoid Valves: A Lyapunov Approach 19

Nonlinear Voltage Control for Motion State Detection in Sole...

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19th International Conference on Methods and Models in Automation and Robotics (MMAR)

作者： Schwab, Manuel Braun, Tristan Straussberger, Florian Reuter, Johannes Univ Appl Sci Konstanz Inst Syst Dynam Constance Germany

ISBN: (纸本)9781479950812

In this paper, a control strategy that enables a reliable dip detection for solenoid valves is presented. For this purpose, the power electronics components are temporarily switched into a linear mode, using a power MOSFET as a voltage controlled resistor. The voltage is stabilized via a nonlinear controller that has been designed using Lyapunov's direct method. The stability region is determined and theoretical investigations are conducted in order to find appropriate controller parameters. The usefulness of the method is demonstrated by several experiments deploying an FPGA based hardware platform.

关键词： Lyapunov methods control system synthesis field programmable gate arrays motion control nonlinear control systems power MOSFET solenoids valves voltage control FPGA based hardware platform Lyapunov approach Lyapunov direct method dip detection field programmable gate array metal oxide semiconductor field effect transistor motion state detection nonlinear controller design nonlinear voltage control power electronics components solenoid valves stability region voltage controlled resistor voltage stability Asymptotic stability MOSFET Resistors Solenoids Stability analysis Valves Voltage control field programmable gate arrays Power MESFETs Voltage regulation Solenoids solenoid valves metal-oxide-semiconductor field effect transistors VALVE gate stability region control system synthesis Nonlinear control systems Lyapunov methods Resistor Device Component Voltage stability EMOSFET Motor Control

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