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An experimental investigation on a multilevel inverter for solar energy applications

INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2013年第1期47卷 157-167页

作者： Chinnaiyan, Venkatachalam Kumar Jerome, Jovitha Karpagam, J. Dr NGP Inst Technol Dept Elect & Elect Engn Coimbatore 641048 Tamil Nadu India PSG Coll Technol Dept Instrumentat & Control Syst Engn Coimbatore 641004 Tamil Nadu India Dr NGP Inst Technol Dept Elect & Commun Engn Coimbatore 641048 Tamil Nadu India

The main objective of the proposed work is to design, develop and test a three phase multilevel inverter with the modern power electronic switches to reduce the power quality issues in solar power conversion system. Due to the increased usage of power electronic converters for processing the power in all walks of our life, the power quality problem become the hot research topic in the recent years. As the power level increases, the voltage level is increased accordingly to obtain satisfactory efficiency. The multilevel power converter has shown growing popularity. The fundamental advantages of multilevel converter topologies are low distorted output waveforms and limited voltage stress on the switching devices and hence the reduced electromagnetic interferences. The main disadvantages are higher complexity and more difficult control;it can be overcome by using modern digital controllers. In this paper, the performance parameters are analyzed with the developed prototype of the three phase cascaded multilevel inverter for solar energy conversion designed with digital controller for reduced power quality issues with three phase AC motor drive. The main objective is to obtain the better quality of output waveform on the inverter output with suitable control strategy on the experimental hardware setup. (c) 2012 Elsevier Ltd. All rights reserved.

关键词： Inverters Power electronics Solar energy Drives Power converters Multi level inverter field programmable gate array

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Enabling Operational Autonomy for Unmanned Aerial Vehicles with Scalability

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JOURNAL OF AEROSPACE INFORMATION SYSTEMS 2013年第11期10卷 517-529页

作者： Jung, Sunghun Ariyur, Kartik B. Purdue Univ Sch Mech Engn W Lafayette IN 47907 USA

A study was conducted to convert a large class of integrated surveillance and reconnaissance (ISR) problems for passive targets in mapped regions to multiple traveling salesman problems (mTSP), which were solved offline to provide several alternative solutions stored offline for online use. The study performed these tasks to enable operational autonomy for unmanned aerial vehicles (UAVs) with scalability. An end-to-end framework was constructed, integrating existing algorithms where available and developing other algorithms to solve this class of problems. The framework incorporated vehicle dynamics and mission constraints so that the genetic algorithm (GA) solving the mTSP only searched feasible solutions. The mTSPs were solved through decomposition into m TSPs, with one for each of the m vehicles.

关键词： UAV Aerospace Information Systems Optimal Control Earth Centered Earth Fixed Satellites field programmable gate array Dijkstra's Algorithm Cyberattack Computing Methods Numerical Integration

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Efficient parallel architecture for implementation of the CMA adaptive antenna

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IETE TECHNICAL REVIEW 2013年第4期30卷 303-312页

作者： Boonpoonga, Akkarat Sirisuk, Phaophak Krairiksh, Monai King Mongkuts Univ Technol North Bangkok Fac Engn Dept Elect & Comp Engn Bangkok 10800 Thailand King Mongkuts Inst Technol Ladkrabang Int Coll Bangkok Thailand King Mongkuts Inst Technol Ladkrabang Fac Engn Bangkok Thailand

This paper presents an efficient parallel architecture for implementation of a constant modulus algorithm (CMA) adaptive array antenna. By inserting delay units into the original CMA, a novel delayed CMA (DCMA) that can significantly reduce the associated critical path is derived. Consequently, a pipelining architecture that supports parallel processing is introduced for implementation of the DCMA. In addition to the pipelining technique, a power-of-two multiplier is proposed for the DCMA leading to the efficient FPGA implementation. The effects of delays and finite word-length on the convergence property of CMA are investigated via simulations. Moreover, the synthesized results demonstrate that FPGA implementation of the proposed architecture using power-of-two arithmetic achieves 26.9% resource reduction in comparison with that of fixed-point arithmetic and operating clock frequency higher than 65 MHz. The implemented FPGA was tested to confirm that the designed architecture operates well for CMA.

关键词： Adaptive antenna Constant modulus algorithm field programmable gate array Pipelining

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Design and implementation of a realtime co-processor for denoising Fiber Optic Gyroscope signal

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DIGITAL SIGNAL PROCESSING 2013年第5期23卷 1813-1825页

作者： Peesapati, Rangababu Sabat, Samrat L. Anumandla, Kiran Kumar Kandyala, Palani Karthik Nayak, Jagannath Univ Hyderabad Sch Phys Hyderabad 500046 Andhra Pradesh India Res Ctr Imarat Hyderabad 500069 Andhra Pradesh India

The amount of noise present in the Fiber Optic Gyroscope (FOG) signal limits its applications and has a negative impact on navigation system. Existing algorithms such as Discrete Wavelet Transform (DWT), Kalman Filter (KF) denoise the FOG signal under static environment, however denoising fails in dynamic environment. Therefore in this paper an Adaptive Moving Average Dual Mode Kalman Filter (AMADMKF) is developed for denoising the FOG signal under both the static and dynamic environments. Performance of the proposed algorithm is compared with DWT and KF techniques. Further, a hardware Intellectual Property (IP) of the algorithm is developed for System on Chip (SoC) implementation using Xilinx Virtex-5 field programmable gate array (Virtex-5FX70T-1136). The developed IP is interfaced as a Co-processor/ Auxiliary Processing Unit (APU) with the PowerPC (PPC440) embedded processor of the FPGA. It is proved that the proposed system is an efficient solution for denoising the FOG signal in real-time environment. Hardware acceleration of developed Co-processor is 65x with respect to its equivalent software implementation of AMADMKF algorithm in the PPC440 embedded processor. (C) 2013 Elsevier Inc. All rights reserved.

关键词： Kalman filter Allan variance analysis field programmable gate array Auxiliary processing unit System on chip

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Current transformer saturation compensation based on a partial nonlinear model

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ELECTRIC POWER SYSTEMS RESEARCH 2013年 97卷 34-40页

作者： Shi, D. Y. Buse, J. Wu, Q. H. Guo, C. X. S China Univ Technol Sch Elect Power Engn Guangzhou 510640 Guangdong Peoples R China Univ Liverpool Dept Elect Engn & Elect Liverpool L69 3GJ Merseyside England Zhejiang Univ Coll Elect Engn Hangzhou 310027 Zhejiang Peoples R China

This paper proposes a partial nonlinear model to accurately represent the nonlinear saturation characteristic of a current transformer (CT). Based on the model, the saturated section of the secondary current as well as the unsaturated section can be used in a regression process to estimate model parameters. The saturated section normally lies near the inception of a fault, therefore accurate parameters can be obtained faster compared with the methods using only unsaturated sections. The pre-fault remanent flux and DC-offset, which could significantly influence CT saturation, are both considered in the model, thus they do not affect the accuracy of the parameter estimation. The computational load of the regression calculation is significantly reduced by using separable nonlinear least squares (SNLLS) method. This provides the feasibility to implement the method for real-time protective relaying. The performance of the method has been evaluated on the data obtained from both PSCAD/EMTDC simulation and live recording with a test CT. The method has also been implemented in a field programmable gate array (FPGA). (C) 2013 Elsevier B.V. All rights reserved.

关键词： Current transformer Saturation Nonlinear regression field programmable gate array

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Firmware Upgrade in xTCA Systems

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2013年第5期60卷 3639-3646页

作者： Makowski, D. Jablonski, G. Perek, P. Mielczarek, A. Predki, P. Schlarb, H. Napieralski, A. Tech Univ Lodz Dept Microelect & Comp Sci PL-90924 Lodz Poland Deutsch Elektronen Synchrotron DESY D-22607 Hamburg Germany

The Advanced Telecommunications Computing Architecture (ATCA) and Micro Telecommunications Computing Architecture (mu TCA) standards, collectively known as xTCA, provide a flexible and scalable infrastructure for designing complex control and data acquisition systems. The xTCA standards are becoming more and more popular in physics applications. programmable devices, such as field programmable gate arrays (FPGAs), conventional and Digital Signal Processors (DSPs) are present in Advanced Mezzanine Card (AMC) modules and ATCA blades used in the xTCA crates. Those devices typically boot from non-volatile memories available on the modules. This paper deals with an universal framework and set of tools for upgrading firmware in such devices in xTCA systems. The proposed framework uses a fat pipe region interface of mu TCA backplane for the firmware data transmission and the Intelligent Platform Management Interface (IPMI) standard for PROM memory management and the control of the upgrade procedure. This is the world's first attempt to implement the firmware upgrade in mu TCA system not using the JTAG Switch Module (JSM).

关键词： Advanced telecommunications computing architecture field programmable gate array firmware upgrade high-energy physics micro telecommunications computing architecture programmable devices

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Resource-efficient and scalable solution to problem of real-data polyphase discrete Fourier transform channelisation with rational over-sampling factor

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IET SIGNAL PROCESSING 2013年第4期7卷 296-305页

作者： Jones, Keith John L3 TRL Technol Head Off Unit 19 Tewkesbury GL20 8DN Glos England

The study describes the results of research carried out into the design of a parallel and resource-efficient solution to the real-data polyphase discrete Fourier transform (DFT), or PDFT. The solution is able to exploit both the real-valued nature of the data and the parallel processing capabilities of the computing technology - assumed to be a field-programmable gate array - to yield a solution with a low size, weight and power requirement. A parallel computing architecture has been devised, based upon batch processing, whereby pipelined operation of the polyphase filter bank (PFB) is achieved using shared resources and pipelined operation of the real-data DFT using the resource-efficient regularised fast Hartley transform (RFHT). The PFB outputs are appropriately re-ordered for input to the RFHT by means of a suitably defined finite state machine. The resulting design, which includes a flexible up-sampling capability (with rational over-sampling factor) to address the problem of adjacent channel interference, trade-off time complexity against space complexity in order to satisfy the associated timing constraints. The solution is also scalable, in terms of the number of channels, so that it might be easily adapted, for new or multiple applications, at minimal re-design effort and cost.

关键词： adjacent channel interference channel bank filters computational complexity discrete Fourier transforms finite state machines Hartley transforms parallel processing resource-efficient solution scalable solution real-data polyphase discrete Fourier transform channelisation rational over-sampling factor PDFT parallel processing capabilities computing technology field programmable gate array parallel computing architecture batch processing pipelined operation polyphase filter bank PFB real-data DFT resource-efficient regularised fast Hartley transform resource-efficient RFHT finite state machine flexible up-sampling capability adjacent channel interference trade-off time complexity space complexity timing constraints adjacent channel interference channel bank filters computational complexity discrete Fourier transforms finite state machines Hartley transforms parallel processing resource-efficient solution scalable solution real-data polyphase discrete Fourier transform channelisation rational over-sampling factor PDFT parallel processing capabilities computing technology field programmable gate array parallel computing architecture batch processing pipelined operation polyphase filter bank PFB real-data DFT resource-efficient regularised fast Hartley transform resource-efficient RFHT finite state machine flexible up-sampling capability adjacent channel interference trade-off time complexity space complexity timing constraints

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Sensor Non Uniformity Correction Algorithms and its Real Time Implementation for Infrared Focal Plane array-based Thermal Imaging System

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DEFENCE SCIENCE JOURNAL 2013年第6期63卷 589-598页

作者： Kumar, Ajay Instruments Res & Dev Estab Dehra Dun 248008 Uttar Pradesh India

The advancement in infrared (IR) detector technologies from 1st to 3rd generation and beyond has resulted in the improvement of infrared imaging systems due to availability of IR detectors with large number of pixels, smaller pitch, higher sensitivity and large F-number. However, it also results in several problems and most serious of them is sensor non-uniformities, which are mainly attributed to the difference in the photo-response of each detector in the infrared focal plane array. These spatial and temporal non-uniformities result in a slowly varying pattern on the image usually called as fixed pattern noise and results in the degradation the temperature resolving capabilities of thermal imaging system considerably. This paper describes two types of non uniformity correction methodologies. First type of algorithms deals with correction of sensor non-uniformities based upon the calibration method. Second type of algorithm deals with correction of sensor non uniformities using scene information present in the acquired images. The proposed algorithms correct both additive and multiplicative non uniformities. These algorithms are evaluated using the simulated & actual infrared data and results of implementations are presented. Furthermore, proposed algorithms are implemented in field programmable gate array based embedded hardware.

关键词： Infrared focal plane array infrared imaging field programmable gate array non uniformities

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Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77 Gbits/s

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MICROELECTRONICS JOURNAL 2013年第9期44卷 744-752页

作者： Mansingka, A. S. Zidan, M. Affan Barakat, M. L. Radwan, A. G. Salama, K. N. KAUST Thuwal 239556900 Saudi Arabia Cairo Univ Fac Engn Dept Engn Math Giza 12211 Egypt

This paper introduces fully digital implementations of four different systems in the 3rd order jerke-quation based chaotic family using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between two system implementations of different bus widths, with up to 100 x higher maximum Lyapunov exponent than the original jerk-equation based chaotic systems. The resulting chaotic output is shown to pass the NISI SR 800-22 statistical test suite for pseudo-random number generators without post-processing by only eliminating the statistically defective bits. The systems are designed in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the native chaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators. (C) 2013 Elsevier Ltd. All rights reserved.

关键词： Chaos Random number generator Lyapunov exponent NIST field programmable gate array

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Fault-Tolerant Five-Leg Converter Topology With FPGA-Based Reconfigurable Control

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2013年第6期60卷 2284-2294页

作者： Shahbazi, Mahmoud Poure, Philippe Saadate, Shahrokh Zolghadri, Mohammad Reza Sharif Univ Technol Tehran Iran Univ Lorraine F-54052 Nancy France Sharif Univ Technol Dept Elect Engn Tehran Iran

Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable controller, and fault detection scheme. For experimental tests, the control and the fault detection and reconfiguration schemes are implemented on a single field-programmable gate array (FPGA) chip. Experimental and simulation results show the effectiveness of the proposed fault-tolerant topology and its FPGA-based control.

关键词： Fault detection fault-tolerant control (FTC) field programmable gate array five-leg converter open-switch fault

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