The quantum key distribution (QKD) system has been developed rapidly, but its key generation rate is limited for kinds of reason such as detector efficiency and not fitted for high speed application such as video conf...
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The quantum key distribution (QKD) system has been developed rapidly, but its key generation rate is limited for kinds of reason such as detector efficiency and not fitted for high speed application such as video conferences. For promotion of key generation rate, an algorithm based secure hash algorithm (SHA) is introduced to process QKD keys which could be expanded to be about tens times and implemented in field programmable gate array (FPGA) device in this paper. The expanded key is tested by NIST test program to verify its randomness and security. In our tests, the expanded keys less than 32 times QKD keys are all passed NIST test program and shows its good security. (C) 2012 Elsevier GmbH. All rights reserved.
As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Current techniques output the r...
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As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for a technique that can trade fault tolerance for lower area penalties. To fill this need, this paper presents a new area constrained approach which accepts available hardware resources as an input and outputs a maximally fault tolerant circuit.
A narrow band radar system based on a field programmable gate array is proposed for dual-mode ***-modulated continuous-wave (FMCW) radar mode is for short-range target detection and pulse-Doppler (PD) radar mode is fo...
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A narrow band radar system based on a field programmable gate array is proposed for dual-mode ***-modulated continuous-wave (FMCW) radar mode is for short-range target detection and pulse-Doppler (PD) radar mode is for long-range target detection. Precomputed codes are used to generate linear frequency modulation signals in both FMCW and PD radar mode. The bandwidths of FMCW and PD radar modes are 10 and 1 MHz. Experiments have been carried out to confirm the system operation. In FMCW radar mode, nonlinear amplitude response can be corrected by precomputed code. In PD radar mode, the RX signals have been checked in the pulse width of 4 mu s with a compressed echo signal response. (C) 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:474479, 2013;View this article online at ***. DOI 10.1002/mop.27343
This paper aims to describe a dedicated high throughput parallel architecture for digital proportional-integral-derivative (PID) controller along with its field programmable gate array (FPGA) and application specific ...
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This paper aims to describe a dedicated high throughput parallel architecture for digital proportional-integral-derivative (PID) controller along with its field programmable gate array (FPGA) and application specific integrated circuit (ASIC) implementations. The processing speed of the controller depends on design of arithmetic units. In this context, this design incorporates parallel multipliers and a parallel adder to enhance the processing speed. This design is deeply pipelined to achieve high throughput. The algorithm is prototyped on Xilinx FPGA and implemented in 180 nm technology using cadence RTL complier. The performance of the controller is analysed by the results from a dc-dc buck converter control system through hardware descriptive language (HDL) co-simulation. Electronic design automation (EDA) simulator link interacts with hardware and software in MATLAB/Simulink environment and in this environment the response of the buck converter control system prior to hardware implementation is shown.
As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Most current techniques output ...
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As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Most current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for area-aware techniques that can trade fault tolerance for lower area penalties. The open question with these approaches is partitioning the circuit into protected and unprotected subsets to maximise the fault coverage. This paper presents several methodologies for selecting subsets and analyses their performances on several circuits based on fault coverage provided, additional latency, and running times.
SRAM-based field programmable gate arrays (SRAM-FPGA) are more and more employed in today's applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upset...
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SRAM-based field programmable gate arrays (SRAM-FPGA) are more and more employed in today's applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upsets, or Single Event Upsets (SEU), which require the adoption of mitigation techniques. In these devices the majority of the configuration memory rules the interconnection setting. In devices employing "switch matrix" routing, the density of interconnections in switch arrays seems to be a critical point. The higher the interconnection density (i.e., the higher the number of interconnection segments activated by the same switch matrix), the higher the probability of an upset due to a configuration bit controlling the switch matrix. This paper presents an approach to estimate the SEU sensitivity of programmable interconnections of SRAM-based FPGAs as a function of the density of programmable interconnection points inside device configurable logic blocks. A probabilistic model of the SEU effects in programmable interconnection points of Xilinx SRAM-FPGAs is described. The application of the proposed approach to a set of sample designs is illustrated.
This paper presents a low cost system based on ultrasound transducers to obtain the localization and orientation information of a mobile node, such as a robot, in a 2D indoor space. The system applies a new differenti...
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This paper presents a low cost system based on ultrasound transducers to obtain the localization and orientation information of a mobile node, such as a robot, in a 2D indoor space. The system applies a new differential time of arrival (DTOA) technique with reduced computational cost, which is called ALO (angle localization and orientation). Instead of directly calculating its position, the system calculates the direction of arrival of the received ultrasonic signal and, through it, its position and orientation. A prototype of a robot has been built in order to show the validity of the method through experimental results. (C) 2013 Elsevier Ltd. All rights reserved.
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. compris...
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ISBN:
(纸本)9781467362405
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement. Ring oscillators used in this work are identical and designed using fast carry logic. The reported improved resolution is attributed to the difference in their frequencies. The novel technique of obtaining difference in their period reduces manual efforts of designer. Two main features of this work are prototyping on a low-cost general purpose FPGA and new low cost verification methodology.
A lowcost Fiber Bragg Grating (FBG) Sensing System based on code division multiplexing access (CDMA) technology is proposed. The system using semiconductor optical amplifier and a broadband source is experimented. Wit...
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ISBN:
(纸本)9780819498168
A lowcost Fiber Bragg Grating (FBG) Sensing System based on code division multiplexing access (CDMA) technology is proposed. The system using semiconductor optical amplifier and a broadband source is experimented. Without a tunable laser source or electro-optic switch driven, the price of system is very low. CDMA is used to separate each reflected sensor. The experimental results show that theory is correct.
The proposed paper deals with Hardware-In-the-Loop (HIL) validation of a 3-phase PWM boost rectifier controller. This validation has been made using field programmable gate array (FPGA) target. The development of the ...
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ISBN:
(纸本)9781479902248
The proposed paper deals with Hardware-In-the-Loop (HIL) validation of a 3-phase PWM boost rectifier controller. This validation has been made using field programmable gate array (FPGA) target. The development of the Real-Time Emulator (RTE) of the power system is firstly discussed. All voltage sources from the grid, filters, power switches and the load real-time models are implemented in hardware using a Xilinx Spartan-6 FPGA device. As for the controller, a PI-based strategy has been chosen to control the DC-link voltage and a Hysteresis-based one for the control of 3-phase line currents. This controller has been implemented in software using the embedded Cortex-M3 processor of SmartFusion FPGA from MicroSemi. Real-time HIL simulation results, as well as offline simulation results are presented and compared.
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