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检索条件"主题词=Field Programmable Gate array"

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Effects of Data's Bit-width on Digital Logic Design

Effects of Data's Bit-width on Digital Logic Design

引用

2nd International Conference on Information Technology and Management Innovation (ICITMI 2013)

作者： Chang, Sheng Cai, Heng Wang, Hao He, Jin Huang, Qijun Wuhan Univ Sch Phys & Technol Dept Elect Sci & Technol Wuhan 430072 Peoples R China Wuhan Univ Inst Microelect & Informat Technol Wuhan 430072 Peoples R China

ISBN: (纸本)9783037858646

Single precision can only achieve 6-7 decimal places, which does not satisfy accuracy demand in many calculations. Double precision can get 13-14 decimal places, but the resource cost is high. In this paper, effects of data bit-width on digital logic design are studied. The accuracy of different bit-width is determined. Then, addition operation, multiplication operation and matrix multiplication with different bit-width are tested on FPGA platform. The results show bit width and circuit design platform have obvious effect on resource cost and circuit efficiency. Finally, a bit-width based circuit design optimization method is proposed.

关键词： bit-width accuracy analysis resource cost field programmable gate array

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Design and Implementation of a 1024-point High-speed FFT Processor Based on the FPGA

Design and Implementation of a 1024-point High-speed FFT Pro...

引用

6th International Congress on Image and Signal Processing (CISP)

作者： Zhou, Sheng Wang, Xiaochun Ji, Jianjun Wang, Yanqun Chinese Acad Med Sci Inst Biomed Engn Tianjin Peoples R China

ISBN: (纸本)9781479927630

To design a Fast Fourier Transform (FFT) processor to meet the needs for high-speed and real-time signal processing. A 1024-point, 32-bit, fixed, complex FFT processor is designed based on a field programmable gate array (FPGA) by using the radix-2 decimation in frequency (DIF) algorithm and the pipeline structure in the butterfly module and the ping-pone operation in data storage unit. When the primary clock is 100 MHz, the 1024-point FFT calculation takes about 62.95 us. The processor is fast enough for processing the high-speed and real time signals. The result provides reference values that theoretical study of the FFT algorithm can be applied into the adaptive dynamic filter of an ultrasonic diagnostic system and an ultrasonic Doppler flow measurement system.

关键词： field programmable gate array 1024-point FFT Butterfly Ping-pong operation Verilog HDL

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Novel field programmable Embryonic Cell for Adder and Multiplier

Novel Field Programmable Embryonic Cell for Adder and Multip...

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9th Conference on Ph D Research in Microelectronics and Electronics (PRIME)

作者： Malhotra, Gayatri Becker, Joachim Ortmanns, Maurits Univ Ulm Inst Microelect D-89081 Ulm Germany

ISBN: (纸本)9781467345811;9781467345804

A novel approach for the implementation of a field programmable embryonic cell is proposed. This is inspired from the concept of cloning used by biological cells to grow a bigger organism. An exemplary full adder and multiplier circuit evolution is simulated using Verilog and verified. An automated generation of configuration data for the embryonic cells from a behavioral description of the overall organism can be done using a genetic algorithm approach in the future.

关键词： Embryonics field programmable gate array Adder Multiplier

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FPGA Implementation of AES-based Crypto Processor

FPGA Implementation of AES-based Crypto Processor

引用

2013 IEEE International Conference on Electronics, Circuits, and Systems

作者： Anwar, Hassan Daneshtalab, Masoud Ebrahimi, Masoumeh Plosila, Juha Tenhunen, Hannu Univ Turku Dept Informat Technol Turku Finland

ISBN: (纸本)9781479924523

Increased demand for data security is an undeniable fact. Towards achieving higher security, cryptographic algorithms play an important role in the protection of data from unapproved usage. In this paper, we present a crypto processor using Advanced Encryption Standard (AES). The AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. The integrated AES module is a fully pipelined module which follows inner round and outer round pipeline design. The results show that the presented pipeline version of the AES algorithm along with MIPS processor outperforms traditional methods. At the operating frequency of 553 MHz, the proposed design can achieve the throughput of 58 Gbps, the latency of 240 ns, and the minimum power consumption of 76 mw.

关键词： Cryptographic field programmable gate array AES pipeline Throughput Pipelining

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Network on Chip for DTMF Decoder and TDM Switching in Telecommunication Network with HDL Environment

Network on Chip for DTMF Decoder and TDM Switching in Teleco...

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3rd IEEE International Advance Computing Conference (IACC)

作者： Kumar, Adesh Singhal, Sonal Kuchhal, Piyush Kumar, Amit Univ Petr & Energy Studies Dept Elect Engn Dehra Dun India Shiv Nadar Univ Dept Elect Engn G B Nagar Uttar Pradesh India Univ Petr & Energy Studies Dept Phys Dehra Dun India Uttaranchal Inst Technol Dehradun Dept Comp Sci Dehra Dun India

ISBN: (纸本)9781467345286

The communication switching system enables the universal connectivity. The universal connectivity is realized when any entity in one part of the world can communicate with any other entity in another part of the world. In many ways telecommunication will acts as a substitute for the increasingly expensive physical transportation. The telecommunication links and switching were mainly designed for voice communication. Traffic handling capacity is an important element of service quality and will therefore play a basic role in this choice Microprocessor/ microcontroller (MPMC) system can handle sequential operations with high flexibility and use of field programmable gate array (FPGA) can handle concurrent operations with high speed in small size area. So combined features of both these systems can enhance the performance of the system. High Performance Hybrid Telephone Network System (HTSS) is designed using combination of stored program control (SPC) and VLSI technology. Touch tone receiver follows DTMF (Dual tone Multifrequency) concept and Time division multiplexing chip is used for the call establishment for inter and intra communication.

关键词： Very High Speed Integrated Circuit Very Large Scale of Integration field programmable gate array Time Division Multiplexing

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A comparison of two embedded programming techniques for high rep rate coherent Doppler lidars

A comparison of two embedded programming techniques for high...

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Conference on Laser Radar Technology and Applications XVIII

作者： Arend, Mark F. Abdelazim, Sameh Lopez, Miguel Moshary, Fred CUNY City Coll Opt Remote Sensing Lab New York NY 10031 USA

ISBN: (纸本)9780819495228

Two FPGA embedded programming approaches are considered and compared for a 20 kHz pulse repetition rate coherent Doppler lidar system which acquires return signals at 400 Msamples/second and operates with signal to noise ratios as low as -20 dB. In the first approach, the acquired return signal is gated in time and the square modulus of the fast Fourier transform is accumulated for each of the range gates, producing a series of power spectra as a function of range. Wind speed decisions based on numerical estimators can then be made after transferring the range gated accumulated power spectra to a host computer, enabling the line of sight wind speed as a function of range gate to be calculated and stored for additional processing. In the second FPGA approach, a digital IQ demodulator and down sampler reduces the data flow requirements so that an autocorrelation matrix representing a pre-selected number of lags can be accumulated, allowing for the process of range gating to be explored on the host computer. The added feature of the second approach is that it allows for an additional capability to adjust the range gate period dynamically as the state of the atmospheric boundary layer ( e. g. backscatter coefficient and stability condition) changes. A simple manual beam scanning technique is used to calculate the wind field vector which is graphically displayed on time-height cross section plots. A comparison to other observed and modeled information is presented suggesting the usefulness for the characterization of microscale meteorology.

关键词： Coherent Doppler lidar wind lidar field programmable gate array autocorrelation FFT Boundary layer

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Real-time interlaced ultrasound and photoacoustic system for in vivo ovarian tissue imaging

Real-time interlaced ultrasound and photoacoustic system for...

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Conference on Photons Plus Ultrasound - Imaging and Sensing

作者： Alqasemi, Umar Li, Hai Yuan, Guangqian Kumavor, Patrick Zanganeh, Saeid Zhu, Quing Univ Connecticut ECE Dept BME Program Storrs CT 06269 USA

ISBN: (纸本)9780819493507

In this paper, we report an ultrafast co-registered ultrasound and photoacoustic imaging system based on FPGA parallel processing. The system features 128-channel parallel acquisition and digitization, along with FPGA-based reconfigurable processing for real-time co-registered imaging of up to 15 frames per second that is only limited by the laser pulse repetition frequency of 15 Hz. We demonstrated the imaging capability of the system by live imaging of a mouse tumor model in vivo, and imaging of human ovaries ex vivo. A compact transvaginal probe that includes the PAT illumination using a fiber-optic assembly was used for this purpose. The system has the potential ability to assist a clinician to perform transvaginal ultrasound scanning and to localize the ovarian mass, while simultaneously mapping the light absorption of the ultrasound detected mass to reveal its vasculature using the co-registered PAT.

关键词： field programmable gate array FPGA-based processing ovarian cancer detection co-registered ultrasound and photoacoustic imaging interlaced acquisition co-registered probe

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Fast Radiographic Image Reconstruction of Moving Object through Gamma Ray Detection using FPGA

Fast Radiographic Image Reconstruction of Moving Object thro...

引用

16th International Multi Topic Conference (INMIC)

作者： Khan, Fayaz Gilani, S. Suleman ICCC Islamabad Pakistan

ISBN: (纸本)9781479930432

Container transport is the major way of freight transportation. In order to assure the safe freight transportation and examine the cargo container non-intrusively for contrabands, the radiation detection technology has been utilized more during last decade. One of the challenging issues in the non-intrusive scanning technology is to improve the scanning speed which can improve the allowable speed of the target. This paper proposes implementation of fast non-intrusive scanning scheme through gamma ray detection using network of 40 field programmable gate array (FPGA) modules. The proposed system is implemented using four Spartan2, 50k gates (FPGA) modules. A real time radiographic image of container is obtained on computer screen, clearly showing the density of the contents of container. Each FPGA module acquires the 16 channel data simultaneously with sampling rate of 52 kilo sample per second (KSPS). The proposed speed of the target is limited to maximum of 46 m/min.

关键词： field programmable gate array Radiation Detection Non-Intrusive Detection Cobalt-60

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A FPGA-Based Data Acquisition System for GEM array detector

A FPGA-Based Data Acquisition System for GEM array detector

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60th IEEE Nuclear Science Symposium (NSS) / Medical Imaging Conference (MIC) / 20th International Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Yen, W. W. Chou, H. P. Natl Tsing Hua Univ Instrumentat Elect & Syst Lab Hsinchu 30013 Taiwan

ISBN: (纸本)9781479905348

In the present study, a data acquisition system for a GEM one-dimensional array detector is presented. The detector system is to measure the trajectory of photoelectrons produced by cosmic rays. The GEM array detector for the present project has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies and pulse shapers. The timing signals and the energy signals are fed to the time-to-digital converter (TDC) units and analog-to-digital converter (ADC) units respectively. The TDC is to measure the time interval between time marks provided by the front-end unit for trajectory information. The measurement of the pulse height for particle energy information is using an amplitude to time convertor (ATC).

关键词： Time-to-Digital Converter field programmable gate array Front-end Electronics Gas Electron Multiplier Detector

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Analysis of a Color Space Conversion Engine Implemented Using Dynamic Partial Reconfiguration

Analysis of a Color Space Conversion Engine Implemented Usin...

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Conference on Color Imaging XVIII - Displaying, Processing, Hardcopy, and Applications

作者： Toukatly, Ryan Patru, Dorin Saber, Eli Peskin, Eric Roylance, Gene Larson, Brad Rochester Inst Technol Rochester NY 14623 USA Hewlett Packard Corp Boise ID USA

ISBN: (纸本)9780819494252

Dynamic Partial Reconfiguration allows parts of a field programmable gate array to be reconfigured, while the rest of the system continues uninterrupted operation. A Color Space Conversion Engine is a digital image-processing pipeline, which requires frequent reconfiguration of some, but not all of its stages. Therefore, it is a digital signal processing system that presumably can take advantage of dynamic partial reconfiguration. This paper describes the necessary design changes, testing, and performance analysis of a color space conversion engine implemented onto a field programmable gate array using dynamic partial reconfiguration. The analysis provides insight into the operational scenarios in which dynamic partial reconfiguration is advantageous or not.

关键词： Dynamic Partial Reconfiguration Color Space Conversion field programmable gate array FPGA Pipeline Image Processing

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