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Workshop on Power Electronics and Power Quality Applications (PEPQA)

作者： Munoz, Juan Osorio, Gustavo Angulo, Fabiola Univ Nacl Colombia Manizales Colombia

ISBN: (纸本)9781479910069;9781479910069

This paper shows experimental results of a boost converter for power factor correction using a quasi sliding control strategy named Zero Average Dynamic (ZAD). After defining the sliding surface, the purpose is obtain a zero average error each period of a PWM control signal, through the computation of a proper duty cycle. The controller was implemented in a FPGA using a DE2-70 board from TERASIC and Quartus II for the design. The experimental setup allows the study of the dynamic behavior. A comparison between simulations and experimental results is presented.

关键词： Power Factor Correction field programmable gate array ZAD Boost converter

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System on Chip Approach for Onboard Computer

System on Chip Approach for Onboard Computer

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IEEE International Conference on Signal Processing, Computing and Control (ISPCC)

作者： Agarwal, Shubham Bhatia, Rajiv Padmavathi, N. Sudhakar, S. Udupa, S. Indian Space Res Org Control Elect Grp ISRO Satellite Ctr Bangalore Karnataka India

ISBN: (纸本)9781467361880;9781467361903

This paper deals with the design and development of a System on chip [SoC] based Onboard Computer [OBC] for future onboard space applications of Indian Space Research Organization [ISRO]. The System on Chip approach shall integrate processor core with associated peripherals, other standard cores like MIL-STD-1553B core, application specific low power digital and analog circuits on a monolithic mixed-signal radiation hardened Application Specific Integrated Circuit [ASIC]. The open source LEON3 Processor core has been chosen for the central processing unit of the SoC after a detailed comparative study. The LEON3 processor has been configured modified, integrated with in-house designed OBC logics and implemented on a Xilinx Virtex 5 FPGA. The SoC can easily interface to other satellite subsystems since a interface for the Mil-Std 1553 Bus has also been designed and implemented. A Floating Point unit has been integrated with the LEON3 pipeline to accelerate the computation of complex floating point algorithms. A closed loop design of the onboard software was executed on the LEON3 processor to obtain a performance gain of nearly 50 when compared to presently used MAR31750 processor.

关键词： field programmable gate array Onboard Computer Processor System on Chip Clock Domain Crossing LEON3 VLSI Space avionics

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Analysis of QR Decomposition for MIMO Systems

Analysis of QR Decomposition for MIMO Systems

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International Conference on Electronic Systems, Signal Processing and Computing

作者： Abha Chauhan Rajesh Mehra ME Student ECE Department NITTTR Chandigarh India Associate Professor ECE Department NITTTR Chandigarh India

ISBN: (纸本)9781479921041

Sphere Decoder (SD) is widely being used in Multiple Input Multiple Output (MIMO) systems to reduce the complexity of the system while obtaining near Maximum Likelihood (ML) performance. The complexity of the system increases with the increase in antenna configuration or the constellation size. Some pre-processing is a fundamental prerequisite in iterative detectors to reduce the system complexity by focusing the received signal energy to reduce the effect of inter-symbol interference. The QR Decomposition (QRD) of communication channel matrices in the pre-processor stage is an important issue to ensure good performance of the subsequent steps of decoding thus a QRD) is commonly used in many MIMO detection algorithms. A sorted QR decomposition (SQRD) is an advanced algorithm that improves the performance of MIMO detection. In this paper the efficiency of QRD and SQRD methods in terms of computational complexity, error rate performance and the FPGA resources utilized is presented. The main contribution of this work is a comparison of hardware implementations of the QRD and SQRD system. QRD for 4x4 MIMO system is implemented on various target FPGA platforms to compare their area utilization.

关键词： Sphere Decoder Maximum likelihood detector Multiple-Input Multiple-Output Pre-Processor QR decomposition Sorted QR decomposition field programmable gate array Bit Error Rate

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INTEGRATION AND CONTROL OF A BATTERY BALANCING SYSTEM

INTEGRATION AND CONTROL OF A BATTERY BALANCING SYSTEM

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作者： Peter L. Norgaard Naval Postgraduate School

学位级别：硕士

The primary focus of this research was the integration of series-loaded resonant (SLR) converters into a field- programmable gate array controlled power converter for use in balancing a series-connected battery bank. As the limits of the power grid are continually extended, the market demand for alternate power sources and energy storage systems will continue to grow. The goal of this research was to build and integrate a bank of SLR converters for use in balancing a series-connected battery bank that is part of a broader system used for power storage and conversion. Voltage and temperature sensors were used to monitor individual cell state-of-charge and rate-of-charge and discharge. Voltage-to-frequency conversion was used to read sensor parameters. A battery balancing algorithm was designed, integrated and demonstrated with experimental results.

关键词： power storage series loaded resonant converter voltage calibration temperature sensing battery balancing field programmable gate array

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A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array

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Journal of Chongqing University 2008年第3期7卷 228-233页

作者：陈永军 College of Electrical and Electronic Engineering Huazhong University of Science and Technology College of Electronics and Information Yangtze University

A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.

关键词： fuzzy control direct torque control field programmable gate array permanent magnet synchronous motor

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Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2013年第3期6卷 12-12页

作者： Liu, Hanyu Rajavel, Senthilkumar T. Akoglu, Ali Univ Arizona Dept Elect & Comp Engn Tucson AZ 85721 USA

In FPGA CAD flow, the clustering stage builds the foundation for placement and routing stages and affects performance parameters, such as routability, delay, and channel width significantly. Net sharing and criticality are the two most commonly used factors in clustering cost functions. With this study, we first derive a third term, net-length factor, and then design a generic method for integrating net length into the clustering algorithms. Net-length factor enables characterizing the nets based on the routing stress they might cause during later stages of the CAD flow and is essential for enhancing the routability of the design. We evaluate the effectiveness of integrating net length as a factor into the well-known timing (T-VPack)-, depopulation (T-NDPack)-, and routability (iRAC and T-RPack)-driven clustering algorithms. Through exhaustive experimental studies, we show that net-length factor consistently helps improve the channel-width performance of routability-, depopulation-, and timing-driven clustering algorithms that do not explicitly target low fan-out nets in their cost functions. Particularly, net-length factor leads to average reduction in channel width for T-VPack, T-RPack, and T-NDPack by 11.6%, 10.8%, and 14.2%, respectively, and in a majority of the cases, improves the critical-path delay without increasing the array size.

关键词： Design Performance Channel width clustering field programmable gate array net length prediction

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Extending the BEAGLE library to a multi-FPGA platform

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BMC BIOINFORMATICS 2013年第1期14卷 1-11页

作者： Jin, Zheming Bakos, Jason D. Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Background: Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple field programmable gate array (FPGA)-based platform called the Convey HC-1. Results: The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 x peak bandwidth x memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a similar to 40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. Conclusions: The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology

关键词： field programmable gate array Memory Bandwidth Memory Controller Target Platform Data Flow Graph

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Reconfiguration-Based Implementation of SVM Classifier on FPGA for Classifying Microarray Data

Reconfiguration-Based Implementation of SVM Classifier on FP...

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Annual International Conference of the IEEE Engineering in Medicine and Biology Society

作者： Hanaa M. Hussain Khaled Benkrid Huseyin Seker Electronics Engineering Department College of Technological Studies The Public Authority of

ISBN: (纸本)9781457702150

Classifying Microarray data, which are of high dimensional nature, requires high computational power. Support Vector Machines-based classifier (SVM) is among the most common and successful classifiers used in the analysis of Microarray data but also requires high computational power due to its complex mathematical architecture. Implementing SVM on hardware exploits the parallelism available within the algorithm kernels to accelerate the classification of Microarray data. In this work, a flexible, dynamically and partially reconfigurable implementation of the SVM classifier on field programmable gate array (FPGA) is presented. The SVM architecture achieved up to 85× speed-up over equivalent general purpose processor (GPP) showing the capability of FPGAs in enhancing the performance of SVM-based analysis of Microarray data as well as future bioinformatics applications.

关键词： Bioinformatics field programmable gate array General Purpose Processor Microarray Support Vector Machine Dynamic Partial Reconfiguration

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A FPGA-Based Data Acquisition System for GEM array detector

A FPGA-Based Data Acquisition System for GEM array detector

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IEEE Nuclear Science Symposium

作者： W. W. Yen H. P. Chou Department of Engineering and System Science National Tsing-Hua University Hsinchu Taiwan

In the present study, a data acquisition system for a GEM one-dimensional array detector is presented. The detector system is to measure the trajectory of photoelectrons produced by cosmic rays. The GEM array detector for the present project has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies and pulse shapers. The timing signals and the energy signals are fed to the time-to-digital converter (TDC) units and analog-to-digital converter (ADC) units respectively. The TDC is to measure the time interval between time marks provided by the front-end unit for trajectory information. The measurement of the pulse height for particle energy information is using an amplitude to time convertor (ATC). The designed TDC has a resolution about 2 ns with good linearity.

关键词： Time-to-Digital Converter field programmable gate array Front-end Electronics Gas Electron Multiplier Detector

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FPGA-based Real-Time Hardware-In-the-Loop validation of a 3-phase PWM Rectifier controller

FPGA-based Real-Time Hardware-In-the-Loop validation of a 3-...

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Annual Conference of the IEEE Industrial Electronics Society

作者： M. Dagbagi A. Hemdani L. Idkhajine M. W. Naouar E. Monmasson I. Slama-Belkhodja Universite de Tunis El Manar ENIT SATIE-IUP GEII

ISBN: (纸本)9781479902255

The proposed paper deals with Hardware-In-the-Loop (HIL) validation of a 3-phase PWM boost rectifier controller. This validation has been made using field programmable gate array (FPGA) target. The development of the Real-Time Emulator (RTE) of the power system is firstly discussed. All voltage sources from the grid, filters, power switches and the load real-time models are implemented in hardware using a Xilinx Spartan-6 FPGA device. As for the controller, a PI-based strategy has been chosen to control the DC-link voltage and a Hysteresis-based one for the control of 3-phase line currents. This controller has been implemented in software using the embedded Cortex-M3 processor of SmartFusion FPGA from MicroSemi. Real-time HIL simulation results, as well as offline simulation results are presented and compared.

关键词： Real time Hardware-In-the-Loop PWM boost rectifier field programmable gate array Real-Time Emulator Associate Discrete Circuit Processor-based controller

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