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IEEE International Conference on Smart Structures and Systems

作者： Mahantesh P Mattada Hansraj Guhilot Department of Electronics &Telecommunication Sanjay Godawat Group of Institutions Kolhapur INDIA Department of Electronics & Communication K.L.E. Society's College of Engineering & Technology Belgaum INDIA

ISBN: (纸本)9781467362429

We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement. Ring oscillators used in this work are identical and designed using fast carry logic. The reported improved resolution is attributed to the difference in their frequencies. The novel technique of obtaining difference in their period reduces manual efforts of designer. Two main features of this work are prototyping on a low-cost general purpose FPGA and new low cost verification methodology.

关键词： Time to Digital Converter TOF Tapped Delay Line field programmable gate array Fluorescence Vernier Delay Line Ring oscillator Ring oscillators field programmable gate arrays FEZF2 gene tapped delay line Fluorescence system clock Identical

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基于FPGA与流比器的损耗电流谐波分量测试系统开发

基于FPGA与流比器的损耗电流谐波分量测试系统开发

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作者：韩加佳哈尔滨理工大学

学位级别：硕士

交联聚乙烯绝缘电力电缆在输配电线路中的应用越来越广泛,已经成为城市电网的主体。水树老化一直是影响交联聚乙烯绝缘电力电缆线路长期运行可靠性的关键因素。为了保证交联聚乙烯绝缘电力电缆的安全运行,有必要开发适应工业现场应用、... 详细信息

交联聚乙烯绝缘电力电缆在输配电线路中的应用越来越广泛,已经成为城市电网的主体。水树老化一直是影响交联聚乙烯绝缘电力电缆线路长期运行可靠性的关键因素。为了保证交联聚乙烯绝缘电力电缆的安全运行,有必要开发适应工业现场应用、操作简单方便的绝缘状态测试系统对其绝缘状态进行诊断。课题组开发的损耗电流谐波分量测试系统,在工程实际应用中被证明是一套有效的测试系统。然而,该设备操作复杂、耗时给操作者带来了不小的麻烦。为此,有必要在该测试系统的基础之上,开发出一套简单易操作的测试系统。本文首先提出了利用可控补偿电流方法实现流比器电桥自动平衡的设计方案,可大大简化设备的操作。在该方案中,由信号采集模块将电压信号和流比器不平衡电流信号同步采集至控制系统中,利用确定的算法计算出需要补偿的电流信号大小,而后通过电压控制电流源产生流经流比器补偿线圈的电流对被测电流进行补偿。补偿效果通过检测线圈的输出来判断,通过不断修正补偿电流信号实现电流比较器的平衡。然后根据安匝平衡原理计算出试品电流的真实信息,此过程通过控制系统自动完成,进而实现谐波分量的自动化测试。确定测试系统设计方案后,对可控补偿电流的算法进行了研究。提出了基于试品非线性模型的可控补偿电流算法,即在FPGA内构建与试品非线性模型相对应的非线性模型,激励电压信号作为FPGA中非线性模型的输入,通过实时操作系统输出补偿电流信号。FPGA中非线性模型系数通过多元线性拟合求得,通过模拟仿真验证了该计算方法的正确性。在软件算法制定好之后,通过LabVIEW软件开发平台,对FPGA和实时控制器进行了软件编程。而后,软件系统与硬件结合搭建了测试系统。最后,以标准介质损耗器作为试品,对测试系统进行了验证性试验。验证性试验证实了测试系统的设计方案是可行的,但测试误差较大,测试系统还有待于进一步修正和完善。

关键词： field programmable gate array 实时测试系统非线性模型

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Interlaced switch boxes placement for three-dimensional FPGA architecture design

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2012年第5期40卷 489-502页

作者： Hsu, Chun-Lung Huang, Yu-Sheng Lee, Fong-Chao Natl Dong Hwa Univ Dept Elect Engn Hualien Taiwan

Three-dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wire-length reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two-dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18-mu m CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM-based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay-power product improvement and 43% area-delay product reduction. Copyright (c) 2010 John Wiley & Sons, Ltd.

关键词： field programmable gate array interlaced delay-power product area-delay product

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A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation

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JOURNAL OF VISUAL COMMUNICATION AND IMAGE REPRESENTATION 2012年第8期23卷 1272-1283页

作者： Barranco, F. Diaz, J. Pino, B. Ros, E. Univ Granada ETSIIT CITIC Dep Arquitectura & Tecnol Comp E-18071 Granada Spain

This paper presents a novel hardware-friendly motion estimation for real-time applications such as robotics or autonomous navigation. Our approach is based on the well-known Lucas & Kanade local algorithm, whose main problem is the unreliability of its estimations for large-range displacements. This disadvantage is solved in the literature by adding the sequential multiscale-with-warping extension, although it dramatically increases the computational cost. Our choice is the implementation of a multiresolution scheme that avoids the warping computation and allows the estimation of large-range motion. This alternative allows the parallel computation of the scale-by-scale motion estimation which makes the whole computation lighter and significantly reduces the processing time compared with the multiscale-with-warping approach. Furthermore, this last fact also means reducing the hardware resource cost for its potential implementation in digital hardware devices such as GPUs, ASICs, or FPGAs. In the discussion, we analyze the speedup of the multiresolution approach compared to the multiscale-with-warping scheme. For an FPGA implementation, we obtain a reduction of latency between 40% and 50% and a resource reduction of 30%. The final solution copes with large-range motion estimations with a simplified architecture very well-suited for customized digital hardware datapath implementations as well as current multicore architectures. (c) 2012 Elsevier Inc. All rights reserved.

关键词： Image motion analysis Optical flow field programmable gate array Architectures for embedded systems Real-time systems Multiscale-with-warping optical flow Efficient multiresolution optical flow Fusion methods for multiresolution optical flow implementaiton

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FPGA-based Personal Authentication Using Fingerprints

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第2期66卷 153-189页

作者： Fons, Mariano Fons, Francisco Canto, Enrique Lopez, Mariano Univ Rovira & Virgili Dept Engn Elect Elect & Automat Tarragona Spain Univ Politecn Cataluna Dept Elect Engn Vilanova I La Geltru Spain

The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.

关键词： Biometrics field programmable gate array Flexible hardware Hardware-software co-design Real-time embedded system Run-time reconfigurable computing

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FPGA-based entropy neural processor for online detection of multiple combined faults on induction motors

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MECHANICAL SYSTEMS AND SIGNAL PROCESSING 2012年 30卷 123-130页

作者： Cabal-Yepez, E. Valtierra-Rodriguez, M. Romero-Troncoso, R. J. Garcia-Perez, A. Osornio-Rios, R. A. Miranda-Vidales, H. Alvarez-Salas, R. Univ Guanajuato Carr Salamanca Valle Div Ingn HSPdigital CA Telemat Procesamiento Digital Senal Guanajuato 36700 Mexico Univ Autonoma Queretaro Fac Ingn HSPdigital CA Mecatron San Juan Del Rio 76807 Queretaro Mexico Zona Univ Univ Autonoma San Luis Potosi Fac Ingn CA Elect Potencia & Control San Luis Potosi 78290 SLP Mexico

For industry, a faulty induction motor signifies production reduction and cost increase. Real-world induction motors can have one or more faults present at the same time that can mislead to a wrong decision about its operational condition. The detection of multiple combined faults is a demanding task, difficult to accomplish even with computing intensive techniques. This work introduces information entropy and artificial neural networks for detecting multiple combined faults by analyzing the 3-axis startup vibration signals of the rotating machine. A field programmable gate array implementation is developed for automatic online detection of single and combined faults in real time. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： Induction motors Multiple combined faults 3-axis vibration signals Information entropy Artificial neural networks field programmable gate array

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Very-large-scale integration design of a low-power and cost-effective context-based adaptive variable length coding decoder for H.264/AVC portable applications

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IET IMAGE PROCESSING 2012年第2期6卷 104-114页

作者： Huang, H-J. Fang, C-H. Fan, C-P. Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chung Hsing Univ Dept Elect Engn Taichung 402 Taiwan

Context-based adaptive variable length coding (CAVLC) is a new and efficient entropy coding tool in H.264/AVC (advanced video coding). This study proposes a low-power and cost-effective CAVLC decoding architecture for the H.264/AVC baseline profile. Specifically, this study proposes an optimum two-layer power model for the variable length look-up table (VLUT) in the CAVLC decoder, and divides the decoding phase of the LUT into two-layer decoding to reduce power consumption. To achieve a cost-effective design, the proposed design merges common codewords to reduce the hardware cost among different LUTs in the second layer decoding. The proposed decoder is based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m CMOS technology, and was completely verified on a field-programmable gate array (FPGA) emulation platform. The proposed design meets the demands of the real-time CAVLC decoding and reduces power consumption by 44-48% more than previous low-power CAVLD schemes. Finally, the proposed low-power and cost-effective CAVLD design is suitable for H.264/AVC portable applications.

关键词： size 0.18 mum Codes table lookup variable length codes field programmable gate arrays Image and video coding entropy codes CMOS technology context-based adaptive variable length coding decoder entropy coding tool common codewords adaptive codes Logic circuits video coding Logic and switching circuits cost-effective CAVLC decoding variable length look-up table advanced video coding H.264/AVC portable applications two-layer decoding decoding CMOS integrated circuits VLSI Video signal processing Taiwan Semiconductor Manufacturing Company field programmable gate array low-power CAVLC decoding power consumption very large scale integration

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Design and implementation of equilateral triangle array digital direction finding system

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IEICE ELECTRONICS EXPRESS 2012年第13期9卷 1102-1108页

作者： Zhou, Lin Wang, Fan Gao, Huotao Sun, Yuxiang Zhang, Huajun Wuhan Univ Elect Informat Dept Wuhan 430072 Peoples R China

In this work, a scheme of an equilateral triangle array digital direction finding system is proposed, which implements the online real-time direction finding task for an airborne system. The three-elements equilateral triangle array can be used for calibrating the channel errors and eliminating the DOA (direction of arrival) fuzzy problem of the two-elements linear array, which is greatly reduced the system complexity and suitable for portable requirement. At the same time, the project adopts field programmable gate array (FPGA) to process the sample data in parallel mode, including data quadrature demodulation and multiple signal classification (MUSIC) algorithm. The hardware implementation of MUSIC algorithm makes the system more flexible and faster than software implementation. The experimental results show that the deviation is less than 0.5 degrees with over 64 snapshots and the time is less 6ms with 256 snapshots, and then the program can complete the MUSIC algorithm accurately with high speed.

关键词： direction of arrival equilateral triangle array channel calibration field programmable gate array multiple signal classification algorithm

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Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第1期69卷 75-85页

作者： He, Ke Crockett, Louise Stewart, Robert Univ Strathclyde EEE Dept Glasgow G1 1XW Lanark Scotland

Partial Reconfiguration (PR) is a method for field programmable gate array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design.

关键词： field programmable gate array Software defined radio Partial reconfiguration Dynamic reconfigurable port 3GPP LTE IEEE 802.16 IEEE 802.11 3GPP WCDMA

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Hardware-software co-design architecture for Joint Photo Expert Graphic XR encoder

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IET IMAGE PROCESSING 2012年第9期6卷 1284-1292页

作者： Tseng, C. -F. Lai, Y. -T. Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

In recent years, because of to the fast growing of internet and digital multi-media, new image compression algorithms are needed to reduce the transferring bandwidth and the decay of image quality. Joint Photo Expert Graphic (JPEG) extended range (XR) is a new standard for still image compression. Compared to previous standards, it provides better image quality and plentiful pixel format. However, the better image quality often comes with the higher computation complexity. In this study, the authors propose a hardware-software co-design architecture for JPEG XR encoder. For photo overlap transform (POT), and photo core transform (PCT), the complicated parts of JPEG XR, the authors propose new algorithms which eliminate data dependency in the basic filters of POT and PCT so that operations can be executed in parallel. The processing rate of the new algorithms is much faster. The authors also demonstrate a basic filter with multiple functions, which can be time-shared by POT and PCT;the hardware cost can be therefore reduced. Moreover, a memory saving scheme is proposed. Therefore the proposed architecture is suitable for stand-alone application-specific integrated circuit (ASIC). In our co-design, POT and PCT are implemented in hardware and then mapped to field programmable gate array (FPGA), whereas the other procedures of JPEG XR such as quantisation are executed by ARM926-EJ processor. The overall performance of our hardware architecture is 50 fps for 4:4:4 HDTV format at 166 MHz.

关键词： frequency 166 MHz image quality ASIC Filtering methods in signal processing photo core transform ARM926-EJ processor data compression hardware-software codesign digital multimedia image compression algorithm JPEG XR encoder field programmable gate arrays Hardware-software codesign Internet Electronic engineering computing FPGA joint photo expert graphic XR encoder Computer vision and image processing techniques computer architecture Image and video coding still image compression application specific integrated circuits image coding hardware architecture photo overlap transform data dependency Integral transforms POT quantisation (signal) Logic circuits Computer architecture computation complexity quantisation JPEG extended range stand-alone application-specific integrated circuit PCT Logic and switching circuits memory saving scheme HDTV format filtering theory filter bandwidth transfer hardware-software co-design architecture field programmable gate array Digital circuit design, modelling and testing transforms

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