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FPGA implementation of a low-power and area-efficient state-table-based compression algorithm for DSLR cameras

TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第6期26卷 2927-2942页

作者： Lone, Mohd Rafi Hakim, Najeeb-ud-Din Natl Inst Technol Dept Elect & Commun Engn Srinagar Jammu & Kashmir India

Small image acquisition devices like digital single lens reflex (DSLR) cameras most commonly use Joint Photographic Expects Group (JPEG) coding standard for lossy compression. Although JPEG is a simple coding standard, its compression efficiency is very low as compared to any typical state-of-the-art image coding standards like set partitioning in hierarchical trees (SPIRT). In this paper, a novel state-table-based SPIRT (STS) algorithm and its field programmable gate array (FPGA) implementation is proposed. The STS uses two small state-tables and two extremely small lists. The STS not only provides better compression efficiency than the state-of-the-art JPEG 2000 at high bit rates but also requires very small memory to hold the state-tables and lists in comparison to SPIRT. On average STS requires 0.86% of the memory needed by SPIRT when evaluated for image sizes ranging from 4 Mpixels to 40 Mpixels. The implementation results show that STS consumes very less FPGA area in comparison to SPIRT-based architectures. The dynamic power dissipation of STS is also less than that of JPEG-like compression standards. This makes our proposed algorithm a better candidate for compression in low-power, low-memory digital image acquisition devices.

关键词： Set partitioning in hierarchical trees very large-scale integration image compression dynamic power dissipation field programmable logic array digital single lens reflex

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field programmable Stateful logic array

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2011年第12期30卷 1800-1813页

作者： Kim, Kyosun Shin, Sangho Kang, Sung-Mo Univ Incheon Dept Elect Engn Inchon 406772 South Korea Univ Calif Santa Cruz Jack Baskin Sch Engn Santa Cruz CA 95064 USA

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, in which general-purpose computation functions can be implemented by configuring only nonvolatile nanowire crossbar switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely, material implication, cannot fan out, a new basic AND operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. The fine-grain ultradeep constant-throughput pipeline properties pose new design automation problems. We address some of the issues, in particular logic representation using OR-inverter graphs, two-level optimization synthesis strategy, data synchronization with data forwarding, stall-free pipelined finite state machines, and constraints for synthesis and mapping onto the fabric.

关键词： field programmable logic array memristive device pipeline architecture stateful logic

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Predicting Statistical Characteristics of Jitter Due to Simultaneous Switching Noise

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IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY 2016年第1期58卷 249-256页

作者： Sui, Chunchun Ren, Liehui Gao, Xu Pan, Jingnan Drewniak, James L. Beetner, Daryl G. Missouri Univ Sci & Technol Dept Elect & Comp Engn Electromagnet Compatibil Lab Rolla MO 65409 USA Cisco Syst Irvine CA 92617 USA

Switching of logic gates is often responsible for significant power supply noise. Predicting the jitter resulting from the power supply noise can be critical to analyze the proper operation of high-speed devices. The statistical characteristics of jitter, such as the mean standard deviation of jitter, can be used to place a meaningful bound on the worst-case timing margin and to estimate the bit error rate. While the statistical characteristics of the noise can be found through simulations of many input logic vectors, such simulations require significant computational effort and require methods for choosing suitable data vectors. Vectorless methods allow rapid analysis of switching without using predefined input data and can be used to understand which portions of the logic circuit contribute most to the noise. In this paper, methods using vectorless techniques are presented to predict the mean and standard deviation of the power supply noise on the printed circuit board (PCB), and the mean and standard deviation of the resulting peak-to-peak jitter in a driver on the same PCB. In experiments, the techniques were able to predict the average and standard deviation of the peak power supply noise on the PCB with 2% and 8% error, respectively, and of the peak-to-peak jitter with 21% error, which is sufficient for predicting how a specific logic design might impact jitter, and for proposing means to minimize that impact.

关键词： Analytical models field programmable logic array integrated circuit (IC) noise jitter noise measurement power distribution statistical analysis

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Design of Encoder and Decoder for Golay code

Design of Encoder and Decoder for Golay code

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International Conference on Communication and Signal Processing

作者： Pallavi Bhoyar Department of Electronics Engineering Yeshwantrao Chavan College of Engineering Nagpur 441110 India

ISBN: (纸本)9781467385497

This paper is based on cyclic redundancy check based encoding scheme. High throughput and high speed hardware for Golay code encoder and decoder could be useful in digital communication system. In this paper, a new algorithm has been proposed for CRC based encoding scheme, which devoid of any linear feedback shift registers (LFSR). In addition, efficient architectures have been proposed for both Golay encoder and decoder, which outperform the existing architectures in terms of speed and throughput. The proposed architecture implemented in virtex-4 Xilinx power estimator. Although the CRC encoder and decoder is intuitive and easy to implement, and to reduce the huge hardware complexity required. The proposed method it improve the transmission system performance level. In this architecture our work is to design a Golay code based on encoder and decoder architecture using CRC generation technique. This technique is used to reduce the circuit complexity for data transmission and reception process.

关键词： Architecture Golay code encoder Golay code decoder field programmable logic array

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The Dynamic Properties Investigation of the PLC CPU Implemented in FPGA

The Dynamic Properties Investigation of the PLC CPU Implemen...

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11th IFAC/IEEE International Conference on programmable Devices and Embedded Systems (PDeS)

作者： Chmiel, M. Hrynkiewicz, E. Silesian Tech Univ Inst Elect Gliwice Poland

ISBN: (纸本)9783902823144

The paper presents some program examples written and tested to show possibilities of construction of CPUs for PLCs build based on FPGA development platform. Presented unit is optimised for minimum response and throughput time. The constructions are based on bit-word structures of CPU and two types of data (condition) exchange methods: with acknowledge and without acknowledge - in both cases control data are passed through the set of flip-flops. Third unit is built to compare with these two. This unit is simple one processor unit which can execute both - binary and numerical operations. The experiments shown high performances of elaborated CPUs.

关键词： programmable logic Controller Central Processing Unit Bit-Word Structure of CPU Scan Time Throughput Time Response Time Concurrent Operation field programmable logic array

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The Dynamic Properties Investigation of the PLC CPU Implemented in FPGA

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IFAC Proceedings Volumes 2012年第7期45卷 151-156页

作者： M. Chmiel E. Hrynkiewicz Institute of Electronics Silesian University of Technology Gliwice

The paper presents some program examples written and tested to show possibilities of construction of CPUs for PLCs build based on FPGA development platform. Presented unit is optimised for minimum response and throughput time. The constructions are based on bit-word structures of CPU and two types of data (condition) exchange methods: with acknowledge and without acknowledge – in both cases control data are passed through the set of flip-flops. Third unit is built to compare with these two. This unit is simple one processor unit which can execute both - binary and numerical operations. The experiments shown high performances of elaborated CPUs.

关键词： programmable logic Controller Central Processing Unit Bit-Word Structure of CPU Scan Time Throughput Time Response Time Concurrent Operation field programmable logic array

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High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC

High parallel-pipeline integer-pel and fractional-pel motion...

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Conference on VLSI Circuits and Systems III

作者： Mora-Campos, Armando Ballester-Merelo, Francisco J. Martinez-Peiro, Marcos A. Canals-Esteve, Jose A. Inst Tecnol Queretaro Dept Elect & Elect Engn Queretaro 76000 Mexico Univ Politecn Valencia Dept Elect Engn Valencia 46022 Spain

ISBN: (纸本)9780819467188

This paper presents efficient integer-pel and fractional-pel motion estimation VLSI architectures for luma video component in H.264/AVC. The proposed architectures were designed as hardware accelerators for 32-bit processors to reduce computation cost and processing time. Both accelerators use the full-search block-matching algorithm to fulfil the standard requirements with maximum quality. The integer motion estimator is composed by a systolic 16x 16 processing elements array with optimal memory management and effective data-path. The array was designed to adjust the search window size and shape at macroblock level without a high control overhead. Simulation results show computing and time reduction from 21.5%, to 60.7% using a search window shape different than square with a maximum PSNR degradation of 0.014 dB. The fractional motion estimation architecture improves time operation of previous designs by means of two parallel-pipeline stages, an effective block flow and faster interpolation modules. The design can process the 41 macroblock partitions and sub-partitions in quarter-pel resolution in 606 clock cycles. Operating at 100-MRz clock frequency, the architecture supports 720p HD video format (c) 30 fps for one reference frame. Implementation results based on FPGA devices using VHDL are included.

关键词： image processing video codecs motion estimation architecture field programmable logic array

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A FPGA-based general purpose multi-sensor data acquisition system with nonlinear sensor characteristic and environment compensation

A FPGA-based general purpose multi-sensor data acquisition s...

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23rd IEEE Instrumentation and Measurement Technology Conference

作者： Martins, Raul Carneiro Ramos, Helena Geirinhas Proenca, Paulo IST DEEC Inst Telecomunicac Av Rovisco Pais P-1049001 Lisbon Portugal

ISBN: (纸本)9780780393592

In this paper a general purpose multi-sensor data acquisition module with broadcasting capabilities and a field programmable logic array (FPGA) at its core is presented. The system, through its FPGA core, has the ability to directly measure sensor impedance and implements a 4(th)-order multivariable polynomial regression (MPR) to model and compensate both each sensor nonlinear characteristic and the influence of the environment, monitored through other connected sensors. An application is shown of a magnetic field transducer with temperature compensation. The sensing element is a magnetoresistance with a nonlinear characteristic of 4% of full scale whose value can vary almost 25% in the experimental operating temperature range (-25 degrees C to 125 degrees C) and a two terminal semiconductor temperature sensor. The application is well adapted to conveniently model strongly non-linear transducer characteristics as it leads to an improvement Of magnetic transducer's accuracy from 25% to well above 1%.

关键词： multivariable polynomial regression modeling and compensation MPR field programmable logic array FPGA calibration error compensation

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REprogrammable FPLA WITH UNIVERSAL TEST SET

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1990年第6期137卷 437-441页

作者： RAJSUMAN, R MALAIYA, YK JAYASUMANA, AP COLORADO STATE UNIV DEPT COMP SCIFT COLLINSCO 80523 COLORADO STATE UNIV DEPT ELECT ENGNFT COLLINSCO 80523

A field programmable logic array is presented which can be programmed. This FPLA uses one-transistor reprogrammable switches instead of fuses. The FPLA design presented here is also easily testable. In this design, the PLA is partitioned into two parts, which are tested independently. The delay is kept to a minimum for each test vector. Furthermore, parallelism is employed during testing, and thus minimal test time is obtained. It employs a universal test set of minimal length to detect all single crosspoint faults, stuck faults and bridging faults. This universal test set also covers the majority of multiple faults. The test set is simple and avoids test generation complexity. A user can reprogram and test the proposed PLA.

关键词： field programmable logic array FPLA logic arrays logic circuits logic testing testable multiple faults logic and switching circuits reprogrammable universal test set

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